公开(公告)号：US20120063228A1

公开(公告)日：2012-03-15

申请号：US13300141

申请日：2011-11-18

申请人： YUNG-FENG LIN ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： YUNG-FENG LIN ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/26

CPC分类号： G11C7/1048 ,  G11C16/28

摘要： Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.

摘要翻译： 通过使用扭曲的数据线和差分感测放大器来减轻耦合到相邻数据线的非易失性存储器中的数据线上的过度擦除感应噪声。 耦合到数据线中的噪声由耦合到参考数据线中的相似噪声补偿并在差分感测放大器中被消除。

公开(公告)号：US08064268B2

公开(公告)日：2011-11-22

申请号：US12564789

申请日：2009-09-22

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： An integrated circuit device includes a serial peripheral interface adapted for receiving a first command supporting an address of a first configuration, wherein the serial peripheral interface supports an address of a second configuration upon receipt of a second command, the second configuration being different from the first configuration. In a specific embodiment, the first and the second configurations are different in address length. In another embodiment, a second address cooperated with the second command has a first part and a second part, the second part comprising a plurality of byte addresses, each of the byte addresses being associated with a corresponding byte of data. In another embodiment, integrated circuit device also includes a mode logic circuit for controlling operations of the first command and the second command. Various other embodiments are also described.

摘要翻译： 集成电路装置包括适于接收支持第一配置的地址的第一命令的串行外围接口，其中，所述串行外设接口在接收到第二命令时支持第二配置的地址，所述第二配置不同于所述第一配置 组态。 在具体实施例中，第一和第二配置的地址长度不同。 在另一个实施例中，与第二命令协作的第二地址具有第一部分和第二部分，第二部分包括多个字节地址，每个字节地址与对应的数据字节相关联。 在另一实施例中，集成电路装置还包括用于控制第一命令和第二命令的操作的模式逻辑电路。 还描述了各种其它实施例。

公开(公告)号：US20110069571A1

公开(公告)日：2011-03-24

申请号：US12816960

申请日：2010-06-16

申请人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C7/00 ,  G11C8/10

CPC分类号： G11C16/16

摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

摘要翻译： 该技术的一个实施例是一种装置，存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

公开(公告)号：US20110068837A1

公开(公告)日：2011-03-24

申请号：US12565624

申请日：2009-09-23

申请人： CHUN-HSIUNG HUNG ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Hsieh-Ming Chih

发明人： CHUN-HSIUNG HUNG ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Hsieh-Ming Chih

IPC分类号： H03L7/00 ,  H03K3/02

CPC分类号： H03K3/00 ,  H03K19/0002 ,  H03K19/09425

摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.

摘要翻译： 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。

公开(公告)号：US20110016288A1

公开(公告)日：2011-01-20

申请号：US12837823

申请日：2010-07-16

申请人： Kuen-Long Chang ,  Yufe-Feng Lin ,  Chun-Hsiung Hung

发明人： Kuen-Long Chang ,  Yufe-Feng Lin ,  Chun-Hsiung Hung

IPC分类号： G06F12/06

CPC分类号： G11C7/10 ,  G06F9/30149 ,  G06F9/342 ,  G06F9/3875

摘要： A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.

摘要翻译： 串行闪存及其地址发送方法。 串行闪速存储器根据第一地址长度选择性地寻址第一存储器空间，或者根据长于第一地址长度的第二地址长度寻址第二存储器空间。 如果根据第一地址长度寻址第一存储器空间，则在地址持续时间内完全接收到第一存储器地址，从而从起始时钟开始输出与第一存储器地址对应的数据。 在地址发送方法中，如果根据第二地址长度寻址第二存储器空间，则在地址持续时间内接收第二存储器地址的一部分。 第二存储器地址的另一部分在等待时间段内被接收，使得对应于第二存储器地址的数据最初从起始时钟输出。

公开(公告)号：US06255900B1

公开(公告)日：2001-07-03

申请号：US09284435

申请日：1999-04-12

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  Tien-Shin Ho ,  I-Long Lee ,  Tzeng-Hei Shiau ,  Ray-Lin Wan

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  Tien-Shin Ho ,  I-Long Lee ,  Tzeng-Hei Shiau ,  Ray-Lin Wan

IPC分类号： G05F110

CPC分类号： G11C16/30 ,  G05F3/242 ,  G11C5/145 ,  G11C16/08 ,  H02M3/07

摘要： An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably about 2 nanoseconds, or less, of the transition in the boost signal.

摘要翻译： 提供了适用于具有低电源电压（例如，2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路。 电压升压电路耦合到电源电压输入和升压信号，该升压信号响应于升压信号的转变而升高集成电路上的节点上的片内电压。 升压电路具有第一模式，其响应于转换而以第一升压速率提升片上电压直到第一阈值，并且响应于转换的第二模式将片上电压提升到第二阈值 升压速率直到第二个阈值。 优选系统中的第二次升压速度比第一次升压速率慢。 检测电路耦合到接收片上电压的集成电路上的节点和电压升压电路。 当节点达到第一阈值时，检测电路向升压电路发信号，当节点达到第二阈值时，信号通知升压电路。 根据本发明的一个方面，在升压信号中的转变的小于5纳秒，更优选约2纳秒或更小的范围内达到第一阈值。

公开(公告)号：US08825978B2

公开(公告)日：2014-09-02

申请号：US13584393

申请日：2012-08-13

申请人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

发明人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

IPC分类号： G06F12/00 ,  G06F13/42 ,  G11C29/00

CPC分类号： G11C7/1072 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104

摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.

摘要翻译： 存储装置包括主机装置和从装置。 主机设备存储验证数据。 从设备包括存储单元，控制单元和逻辑单元。 控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。 逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。 前导码数据和存储数据根据内部时钟信号发送。 主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

公开(公告)号：US08599640B2

公开(公告)日：2013-12-03

申请号：US13708150

申请日：2012-12-07

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh Ming Chih

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh Ming Chih

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12

摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.

摘要翻译： 存储器集成电路具有访问存储器集成电路的存储单元的控制电路。 控制电路响应于包括第一命令和第二命令的命令。 第一个命令指定高位地址位集合。 第二个命令指定低位地址位集合。 地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。 第一个命令和第二个命令在命令代码中有所不同。

公开(公告)号：US20130279265A1

公开(公告)日：2013-10-24

申请号：US13453312

申请日：2012-04-23

申请人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/344

摘要： Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

摘要翻译： 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

公开(公告)号：US08542536B2

公开(公告)日：2013-09-24

申请号：US13539831

申请日：2012-07-02

申请人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/28

摘要： A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the memory cell responds as a programmed memory cell in response to one of the sets of conditions, but responds as an erased memory cell in response to another of the sets of conditions.

摘要翻译： 一种检测存储器单元的干扰状况的方法包括将多组条件应用于存储单元，并根据条件集确定存储单元是否作为编程存储器单元。 如果存储器单元响应于一组条件而作为编程存储器单元进行响应，则可以检测到干扰的存储器单元，而是响应于另一组条件而被响应为擦除存储器单元。