公开(公告)号：US07570541B2

公开(公告)日：2009-08-04

申请号：US11488024

申请日：2006-07-18

申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C7/1018 ,  G11C7/1042 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085

摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

摘要翻译： 字控制电路激活对应于连续模式重叠的起始行地址和下一行地址的字线。 因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。 可以按顺序的方式访问连接到不同字线的存储单元。 也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。 这可以防止数据传输速率降低。 此外，不需要形成用于通知控制器正在切换字线的事实的信号和控制电路，使得可以简化控制器的半导体存储器件和控制电路的结构。 这导致系统成本的降低。

公开(公告)号：US20090010080A1

公开(公告)日：2009-01-08

申请号：US12201922

申请日：2008-08-29

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C7/00 ,  G11C5/14 ,  G11C8/00

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。

公开(公告)号：US07394709B2

公开(公告)日：2008-07-01

申请号：US11024734

申请日：2004-12-30

申请人： Kaoru Mori ,  Shinya Fujioka

发明人： Kaoru Mori ,  Shinya Fujioka

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C5/147 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/5006 ,  G11C2211/4065 ,  G11C2211/4067

摘要： A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.

摘要翻译： 提供了一种存储器件，其具有：用于存储数据的存储器单元; 一个字线选择存储单元; 可选择的存储单元的位线; 预充电电源，用于向位线提供预充电电压; 预充电电路，用于将预充电电源连接到或从所述位线断开; 以及电流限制元件，用于根据操作状态至少两步地控制在预充电电源和位线之间流动的电流的大小。

公开(公告)号：US07239569B2

公开(公告)日：2007-07-03

申请号：US11488785

申请日：2006-07-19

申请人： Shinya Fujioka ,  Kotoku Sato

发明人： Shinya Fujioka ,  Kotoku Sato

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C11/40603 ,  G11C11/40615

摘要： A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.

摘要翻译： 提供保持与从外部提供的访问请求相关的信息的解码结果和地址寄存器的命令寄存器，并且在处理电路即芯片控制电路中解码与来自外部的访问请求有关的信息， 一个地址解码器和一个由访问控制电路对应于存储单元阵列中的外部访问请求的操作可以独立地并行执行，从而可以多次输入来自外部的访问请求，并且可以实现流水线操作 解码和对应于存储单元阵列中的外部访问请求的操作，从而使得可以加速对半导体存储器件的访问操作而不引起任何问题。

公开(公告)号：US06759866B2

公开(公告)日：2004-07-06

申请号：US10274602

申请日：2002-10-22

申请人： Katsuhiro Mori ,  Shinya Fujioka

发明人： Katsuhiro Mori ,  Shinya Fujioka

IPC分类号： G01R3128

CPC分类号： G01R31/3004 ,  G01R31/31721

摘要： Operating margins of a semiconductor integrated circuit are reliably tested at low power consumption by switching power supply circuits between normal operation mode wherein a first step-up power supply serves both memory core and a step-down power supply, and testing mode wherein the memory core is powered by an external testing power supply that provides a fluctuating voltage for testing, and the step-down power supply is served by a second step-up power supply.

摘要翻译： 半导体集成电路的工作裕度通过在正常操作模式之间切换电源电路而被可靠地测试，其中第一升压电源用于存储器核心和降压电源，以及测试模式，其中存储器核心 由外部测试电源供电，为测试提供波动的电压，降压电源由第二升压电源供电。

公开(公告)号：US06731553B2

公开(公告)日：2004-05-04

申请号：US10270196

申请日：2002-10-15

申请人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara

发明人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara

IPC分类号： G11C700

CPC分类号： G11C29/40

摘要： A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=L×M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.

摘要翻译： 多比特输出配置存储器电路包括：具有正常单元阵列的存储器核心和具有多个存储单元的冗余单元阵列; N个输出端子，分别输出从存储器芯读出的N位输出; 输出电路，设置在输出端子和存储器核心之间，其检测从所述存储器芯片读出的N位输出（N = L×M）的每个L位输出是否匹配，并输出成为输出的压缩输出 在匹配的情况下的数据在不匹配的情况下变为第三状态时，输出到N个输出端的第一输出端。 响应多个测试命令或外部终端的测试控制信号中的每一个，M个组的L位输出的压缩输出以时间共享的形式被输出。

公开(公告)号：US06721910B2

公开(公告)日：2004-04-13

申请号：US09400831

申请日：1999-09-21

申请人： Kazuhiro Ninomiya ,  Shinya Fujioka ,  Yasuharu Sato

发明人： Kazuhiro Ninomiya ,  Shinya Fujioka ,  Yasuharu Sato

IPC分类号： G11C2900

CPC分类号： G11C5/063 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

摘要： A synchronous DRAM (SDRAM) or a fast cycle RAM (FCRAM) includes capacitors connected by switches to a signal wire. The switches are controlled to connect and disconnect the capacitors to the signal wire. In a test mode, the transmission time of a control signal is tested by connecting various combinations of the capacitors to the signal wire, and then measuring the signal timing. The signal timing of the memory device can be controlled by selecting which and how many of the capacitors are connected to the signal wire.

摘要翻译： 同步DRAM（SDRAM）或快速周期RAM（FCRAM）包括通过开关连接到信号线的电容器。 控制开关将电容器连接到信号线。 在测试模式下，通过将各种电容器的组合连接到信号线，然后测量信号时序来测试控制信号的传输时间。 可以通过选择哪个和多少电容器连接到信号线来控制存储器件的信号定时。

公开(公告)号：US06683491B2

公开(公告)日：2004-01-27

申请号：US10106107

申请日：2002-03-27

申请人： Toru Koga ,  Shinya Fujioka ,  Katsuhiro Mori

发明人： Toru Koga ,  Shinya Fujioka ,  Katsuhiro Mori

IPC分类号： G05F110

CPC分类号： G11C11/4074 ,  G11C2207/2227

摘要： First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.

摘要翻译： 第一和第二电压发生器产生分别提供给第一内部电源线和第二内部电源电压的第一内部电源电压以供给第二内部电源线。 当第一和第二电压发生器的操作被暂停时，短路使第一和第二内部电源线短路。 第一和第二内部电源线变为浮动，并且各个内部电源线中存储的电荷逐渐排出。 这里，由于电荷被重新分配给两个内部电源线，所以第一和第二内部电源电压随着它们的下降而变得相等。 因此，可以防止第一和第二内部电源电压反转，并且可以防止连接到第一和第二内部电源线的内部电路发生故障。

公开(公告)号：US06459641B2

公开(公告)日：2002-10-01

申请号：US09834945

申请日：2001-04-16

申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

摘要翻译： 本发明的目的在于提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

公开(公告)号：US06246620B1

公开(公告)日：2001-06-12

申请号：US09533759

申请日：2000-03-23

申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.