公开(公告)号：US09000853B1

公开(公告)日：2015-04-07

申请号：US13849999

申请日：2013-03-25

Applicant: Integrated Device Technology, Inc.

Inventor： Nelson Arata ,  Harmeet Bhugra

IPC: H03B5/30 ,  H03L7/16 ,  H03B5/18

CPC classification number: H03B5/1852 ,  H03B5/30 ,  H03L7/197

Abstract: Integrated circuit devices include a packaged MEMS-based oscillator circuit, which is configured to support bidirectional frequency margining of a periodic output signal. This bidirectional frequency margining is achieved using a first signal to synchronize changes in a frequency of the periodic output signal and a second signal to control whether the changes in the frequency of the periodic output signal are incremental or decremental. In particular, the oscillator circuit may be configured so that each change in the frequency of the periodic output signal is synchronized to a corresponding first voltage transition of the first signal and a voltage level of the second signal may be used to control whether the changes in the frequency of the periodic output signal are incremental or decremental.

Abstract translation: 集成电路器件包括封装的基于MEMS的振荡器电路，其被配置为支持周期性输出信号的双向频率裕度。 使用第一信号来实现该双向频率裕度，以使周期性输出信号的频率的变化同步第二信号，以控制周期性输出信号的频率的变化是递增的还是递减的。 特别地，振荡器电路可以被配置为使得周期性输出信号的频率的每个变化被同步到第一信号的对应的第一电压转换，并且第二信号的电压电平可以用于控制是否改变 周期性输出信号的频率是递增或递减的。

公开(公告)号：US08989257B1

公开(公告)日：2015-03-24

申请号：US14050130

申请日：2013-10-09

Applicant: Integrated Device Technology, Inc.

Inventor： Mohammad Shahanshah Akhter ,  Brian Scott Darnell ,  Steve Lamontagne ,  Bachir Berkane

IPC: H04B1/66 ,  H03M7/30

CPC classification number: H03M7/6041 ,  H03M7/3059

Abstract: The method and apparatus of the present invention provides for the compression of signal data having a low latency jitter while maintaining a target compression ratio and reasonable degradation, as is required by next generation systems. In accordance with the present invention, a method and apparatus are provided for compressing data in a communication system by receiving uncompressed packet at a compressor of the communication system, segmenting the packet into a plurality of packet segments, calculating signal sample bit-removal information for each of the plurality of packet segments and compressing the packet segments utilizing the signal sample bit-removal information that is calculated based upon the signal characteristics of the uncompressed packet and a desired target compression ratio.

Abstract translation: 本发明的方法和装置提供了对具有低等待时间抖动的信号数据的压缩，同时保持目标压缩比和合理的劣化，如下一代系统所要求的那样。 根据本发明，提供了一种用于在通信系统中通过在通信系统的压缩器处接收未压缩分组来压缩数据的方法和装置，将分组分割成多个分组段，计算信号样本比特消除信息 多个分组段中的每一个，并且利用基于未压缩分组的信号特性和期望的目标压缩比计算的信号样本比特去除信息来压缩分组分段。

公开(公告)号：US08989088B2

公开(公告)日：2015-03-24

申请号：US13476862

申请日：2012-05-21

Applicant: Yi Ling

Inventor： Yi Ling

IPC: H04W4/00 ,  H04J11/00 ,  H04W88/08 ,  H03M7/30 ,  H04L27/26

CPC classification number: H04W88/085 ,  H03M7/30 ,  H04L27/2607 ,  H04L27/265

Abstract: A method and apparatus provides OFDM signal compression for transfer over serial data links in a base transceiver system (BTS) of a wireless communication network. For the uplink, an RF unit of the BTS applies OFDM cyclic prefix removal and OFDM frequency transformation of the baseband signal samples followed by frequency domain compression of the baseband signal samples, resulting from analog to digital conversion of received analog signals followed by digital downconversion, forming compressed coefficients. After transfer over the serial data link, the baseband processor applies frequency domain decompression to the compressed coefficients prior to further signal processing. For the downlink, the RF unit performs frequency domain decompression of the compressed coefficients and applies OFDM inverse frequency transformation of the decompressed coefficients and OFDM cyclic prefix insertion prior to digital upconversion and digital to analog conversion, generating the analog signal for transmission over the antenna.

Abstract translation: 方法和装置提供用于在无线通信网络的基站收发器系统（BTS）中的串行数据链路上进行传输的OFDM信号压缩。 对于上行链路，BTS的RF单元对基带信号样本进行OFDM循环前缀去除和OFDM频率变换，随后是基带信号采样的频域压缩，由接收的模拟信号的模数转换，随后进行数字下变频， 形成压缩系数。 在通过串行数据链路传输之后，基带处理器在进一步信号处理之前对压缩系数应用频域解压缩。 对于下行链路，RF单元执行压缩系数的频域解压缩，并且在数字上变频和数模转换之前应用解压缩系数和OFDM循环前缀插入的OFDM逆频变换，生成模拟信号以在天线上传输。

公开(公告)号：US20150035372A1

公开(公告)日：2015-02-05

申请号：US13958389

申请日：2013-08-02

Applicant: Integrated Device Technology, Inc.

Inventor： Ovidiu Aioanei

IPC: H02J7/02 ,  H02J5/00

CPC classification number: H02J50/12 ,  H02J5/005 ,  H02J7/0004 ,  H02J7/025 ,  H02J50/60

Abstract: A wireless power receiver comprises a resonant tank configured to generate an AC power signal responsive to an electromagnetic field, a rectifier configured to receive the AC power signal and generate a DC output power signal, and control logic configured to control the resonant tank to reconfigure and adjust its resonant frequency responsive to a determined transmitter type of a wireless power transmitter. The control logic may operate the wireless power receiver as a multimode receiver having a first mode for a first transmitter type and a second mode for a second transmitter type. The resonant tank may exhibit a different resonant frequency for each of the first mode and the second mode. A method comprises determining a transmitter type for a wireless power transmitter desired to establish a mutual inductance relationship, and adjusting a resonant frequency of a resonant tank of a wireless power receiver.

Abstract translation: 一种无线电力接收机包括：谐振槽，被配置为产生响应于电磁场的AC电力信号;整流器，被配置为接收AC电力信号并产生DC输出功率信号，以及控制逻辑，被配置为控制谐振回路重新配置， 响应于所确定的无线电力发射机的发射机类型来调节其谐振频率。 控制逻辑可以将无线电力接收机作为具有用于第一发射机类型的第一模式和用于第二发射机类型的第二模式的多模接收机操作。 对于第一模式和第二模式中的每一个，谐振槽可以呈现不同的谐振频率。 一种方法包括确定期望建立互感关系的无线功率发射机的发射机类型，以及调整无线功率接收机的谐振频率的谐振频率。

公开(公告)号：US20140265610A1

公开(公告)日：2014-09-18

申请号：US13801953

申请日：2013-03-13

Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.

Inventor： Anton Bakker ,  Craig Lambert

IPC: H02J7/02 ,  H04B5/00

CPC classification number: H04B5/0037 ,  G05B13/0205 ,  H02J5/005 ,  H02J7/025 ,  H02J17/00 ,  H02J50/12 ,  H02J50/60 ,  H02M7/219 ,  H04B5/0031 ,  Y02B70/1441

Abstract: A wireless power enabled apparatus may comprise a wireless power receiver that includes a receive coil configured to generate an AC signal responsive an electromagnetic field, a rectifier including a plurality of switches configured to receive the AC signal and generate an output power signal, and control logic configured to control the plurality of switches to cause the rectifier to modulate the output power signal. The control logic may be configured to control the plurality of switches within the rectifier to have an overlap delay that modulates at least one parameter of the wireless power receiver. A method of operating a receiver side of a wireless power transfer system comprises generating an output power signal including a rectified voltage and a rectified current responsive to receiving a wireless power signal, and controlling a rectifier according to at least one mode including a power modulation mode modulating the output power signal.

Abstract translation: 一种启用无线功率的设备可以包括无线功率接收器，其包括被配置为产生响应于电磁场的AC信号的接收线圈，整流器，包括被配置为接收AC信号并产生输出功率信号的多个开关，以及控制逻辑 被配置为控制所述多个开关以使所述整流器调制所述输出功率信号。 控制逻辑可以被配置为控制整流器内的多个开关以具有调制无线电力接收器的至少一个参数的重叠延迟。 一种操作无线电力传输系统的接收器侧的方法包括响应于接收无线电力信号而产生包括整流电压和整流电流的输出功率信号，以及根据包括功率调制模式的至少一种模式来控制整流器 调制输出功​​率信号。

公开(公告)号：US08803622B1

公开(公告)日：2014-08-12

申请号：US13629732

申请日：2012-09-28

Applicant: Integrated Device Technology, Inc.

Inventor： Minhui Yan ,  Chien-Chen Chen ,  Harmeet Bhugra

IPC: H03B5/36

CPC classification number: H03B5/36 ,  H03B5/06

Abstract: Oscillator circuits include a MEMs resonator, a variable impedance circuit (e.g., varistor) and an adjustable gain amplifier. The variable impedance circuit includes a first terminal electrically coupled to a first terminal of the MEMs resonator and the adjustable gain amplifier is electrically coupled to the variable impedance circuit. The adjustable gain amplifier may have an input terminal electrically coupled to the variable impedance circuit and a second terminal of the MEMs resonator may receive, as feedback, a signal derived from an output of the adjustable gain amplifier. A Q-factor control circuit may be provided, which is configured to drive the variable impedance circuit and the adjustable gain amplifier with first and second control signals, respectively, that cause an impedance of the variable impedance circuit and a gain of the adjustable gain amplifier to be relatively high during a start-up time interval and relatively low during a post start-up time interval.

Abstract translation: 振荡器电路包括MEM谐振器，可变阻抗电路（例如，变阻器）和可调增益放大器。 可变阻抗电路包括电耦合到MEM谐振器的第一端子的第一端子，并且可调增益放大器电耦合到可变阻抗电路。 可调增益放大器可以具有电耦合到可变阻抗电路的输入端子，并且MEM谐振器的第二端子可以接收从可调增益放大器的输出导出的信号作为反馈。 可以提供Q因子控制电路，其被配置为分别引起可变阻抗电路的阻抗和可调增益放大器的增益的第一和第二控制信号驱动可变阻抗电路和可调增益放大器 在启动时间间隔期间相对较高，并且在后启动时间间隔期间相对较低。

公开(公告)号：US08773096B2

公开(公告)日：2014-07-08

申请号：US13434612

申请日：2012-03-29

Applicant: Shawn Wang ,  Yumin Zhang ,  Jeffrey G. Barrow

Inventor： Shawn Wang ,  Yumin Zhang ,  Jeffrey G. Barrow

IPC: G05F1/40 ,  G05F1/44

CPC classification number: G05F1/575

Abstract: A voltage regulator includes an amplifier to generate a difference voltage responsive to a comparison of a reference voltage and a feedback voltage. An output driver is coupled to the amplifier and drives a regulated output voltage responsive to the difference voltage. An impedance circuit is coupled between the output driver and a low power source and establishes the feedback voltage responsive to a current through the impedance circuit. A variation detector is operably coupled between the regulated output voltage and the difference voltage and is configured to modify the difference voltage. In some embodiments, the difference voltage is modified responsive to a rapid change of the regulated output voltage capacitively coupled to the variation detector. In other embodiments, the difference voltage is modified responsive to a rapid change of the feedback voltage capacitively coupled to the variation detector.

Abstract translation: 电压调节器包括响应于参考电压和反馈电压的比较而产生差分电压的放大器。 输出驱动器耦合到放大器并响应于差分电压驱动稳定的输出电压。 阻抗电路耦合在输出驱动器和低电源之间，并响应于通过阻抗电路的电流建立反馈电压。 变异检测器可操作地耦合在调节的输出电压和差分电压之间，并且被配置为修改差分电压。 在一些实施例中，响应于电容耦合到变化检测器的稳压输出电压的快速变化来修改差分电压。 在其他实施例中，响应于电容耦合到变化检测器的反馈电压的快速变化来修改差分电压。

公开(公告)号：US08769329B1

公开(公告)日：2014-07-01

申请号：US13214068

申请日：2011-08-19

Applicant: Cheng Wen Hsiao ,  Eric Leung

Inventor： Cheng Wen Hsiao ,  Eric Leung

IPC: G06F1/00 ,  B23K11/24 ,  G06F3/038 ,  H02M1/00 ,  G01R15/00 ,  G06F13/00

CPC classification number: G06F1/266 ,  G06F1/26

Abstract: A peripheral power management system includes a power monitor for determining a power consumption characteristic of a computing processor and a controller for generating a reference power signal based on the power consumption characteristic. The peripheral power management system also includes a power regulator control signal generator for generating a power regulator control signal based on the reference power signal. The power regulator control signal controls a peripheral device power regulator which regulates an electrical supply power of a peripheral device. In this way, the peripheral power management system controls regulation of the electrical supply power of the peripheral device based on the power consumption characteristic of the computing processor. In some embodiments, the peripheral power management system determines the power consumption characteristic of the computing processor by monitoring communication on a serial voltage identification bus.

Abstract translation: 外围电源管理系统包括用于确定计算处理器的功耗特性的功率监视器和用于基于功耗特性产生参考功率信号的控制器。 外围电源管理系统还包括功率调节器控制信号发生器，用于基于参考功率信号产生功率调节器控制信号。 电源调节器控制信号控制外围设备电源调节器，其调节外围设备的电源功率。 以这种方式，外围电源管理系统基于计算处理器的功耗特性来控制对外围设备的电力供应的调节。 在一些实施例中，外围电源管理系统通过监视串行电压识别总线上的通信来确定计算处理器的功耗特性。

公开(公告)号：US08750006B2

公开(公告)日：2014-06-10

申请号：US12649301

申请日：2009-12-29

Applicant: Andrey Malinin ,  Anatoly Cherepakhin ,  Eric Allan Larson

Inventor： Andrey Malinin ,  Anatoly Cherepakhin ,  Eric Allan Larson

IPC: H02M7/217

CPC classification number: H02M3/33592 ,  H01F27/40 ,  H02M7/217 ,  Y02B70/1475

Abstract: A synchronous rectifier circuit rectifies an AC input voltage to produce a DC output voltage. The synchronous rectifier circuit comprises MOSFET (metal-oxide-semiconductor field-effect transistor) switches coupled within secondary transformer windings resulting in a shortened AC current path compared to conventional synchronous rectifier circuits. The shortened current path mitigates skin and proximity effects, substantially improving the power efficiency of the synchronous rectifier circuit. A rectifier assembly integrates one or more synchronous rectifier circuits within a magnetic core.

Abstract translation: 同步整流电路整流交流输入电压以产生直流输出电压。 同步整流电路包括耦合在次级变压器绕组内的MOSFET（金属氧化物半导体场效应晶体管），导致与传统的同步整流电路相比缩短的AC电流路径。 缩短的电流路径减轻了皮肤和邻近效应，大大提高了同步整流电路的功率效率。 整流器组件将一个或多个同步整流电路集成在磁芯内。

公开(公告)号：US08612503B2

公开(公告)日：2013-12-17

申请号：US12724510

申请日：2010-03-16

Applicant: Manoj Gunwani ,  Harekrishna Verma

Inventor： Manoj Gunwani ,  Harekrishna Verma

IPC: G06F17/10

CPC classification number: H03K19/177

Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.

Abstract translation: 信号处理引擎（SPE）包括用于分别从前向延迟链和反向延迟链产生可选择的前向抽头和可选择反向抽头的电路。 加法/减法单元将可选择的正向抽头和可选择的反向抽头算术组合以产生中间输出。 乘法器将中间输出和来自圆形系数缓冲器的系数输出相结合以产生乘法结果。 另一个加法器/减法器将乘法结果与包括经处理的输入或累加器反馈的第二项组合，通过使用乘法结果旁路，相加或减去第二项以产生累加器输出。 累加器输出可以延迟可编程的时钟周期数以产生经处理的输出。 在一些实施例中，SPE通过可编程SPE路由块耦合到形成可编程逻辑阵列的可编程逻辑块。