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311 条记录 (耗时 0.014 秒)

    Trigger and oscillation system
    63.
    发明授权
    Trigger and oscillation system 有权

    公开(公告)号：US10014847B2

    公开(公告)日：2018-07-03

    申请号：US15654795

    申请日：2017-07-20

    申请人： SHENZHEN GOODIX TECHNOLOGY CO., LTD.

    发明人： Mengwen Zhang

    IPC分类号： H03K3/3565 ,  H03B5/36 ,  H03K3/012

    CPC分类号： H03K3/3565 ,  H03B5/06 ,  H03B5/36 ,  H03B5/362 ,  H03B5/364 ,  H03B2200/0012 ,  H03B2200/0066 ,  H03B2201/031 ,  H03K3/012 ,  H03L3/00

    摘要： A trigger, includes: a first voltage input terminal; a bias voltage input terminal; a first bias transistor having a scaling of N to a first component of an external device; a comparator transistor having a scaling of N to a second component of the external device; a first switch transistor and a second switch transistor; a shunt transistor having a control terminal connected to the first voltage input terminal, a second terminal connected to the second terminal of the second switch transistor, and a first terminal connected to the first terminal of the comparator transistor. The shunt transistor has an enlarging scale of M to the comparator transistor. A voltage output terminal is respectively connected to the second terminal of the first switch transistor, the control terminal of the second switch transistor, and the second terminal of the comparator transistor.

    Drive circuit for an oscillator
    64.
    发明授权
    Drive circuit for an oscillator 有权

    公开(公告)号：US10003301B2

    公开(公告)日：2018-06-19

    申请号：US15270652

    申请日：2016-09-20

    申请人： The Swatch Group Research and Development Ltd

    发明人： Massimiliano Bracco

    IPC分类号： H03B5/08 ,  H03B5/32 ,  H03K3/02 ,  H03B5/06 ,  H03K21/38

    CPC分类号： H03B5/32 ,  H03B5/06 ,  H03B5/364 ,  H03K3/02 ,  H03K21/38

    摘要： The present invention concerns a drive circuit for driving an oscillator. The drive circuit comprises a first inductor comprising a first terminal and a second terminal; an electrical energy source connected to the first terminal; and a switching circuit connected to the second terminal and to the oscillator. The switching circuit is configured to operate at least in an off state, where it is configured not to feed electrical energy to the oscillator, and in an on state, where it is configured to feed electrical energy to the oscillator. The first inductor is arranged to store energy in its magnetic field when the switching circuit is in the off state, and, when the switching circuit is in the on state, the switching circuit is arranged to use at least some of the energy stored in the magnetic field to deliver a surge of current from the electrical energy source to the oscillator.

    FREQUENCY SYNTHESIZERS WITH ADJUSTABLE DELAYS
    67.
    发明申请
    FREQUENCY SYNTHESIZERS WITH ADJUSTABLE DELAYS 有权
    具有可调延迟的频率合成器

    公开(公告)号：US20170063387A1

    公开(公告)日：2017-03-02

    申请号：US14836797

    申请日：2015-08-26

    申请人： NXP B.V.

    发明人： Yuan Gao ,  Frank Leong ,  Robert Bogdan Staszewski

    IPC分类号： H03L7/197 ,  H03L7/099 ,  H03K5/13

    CPC分类号： H03L7/1974 ,  H03B5/06 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1234 ,  H03B5/124 ,  H03B5/1268 ,  H03K5/131 ,  H03K2005/00058 ,  H03L3/00 ,  H03L5/00 ,  H03L7/099 ,  H03L7/0992 ,  H03L7/18 ,  H03L2207/06 ,  H03L2207/50

    摘要： A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.

    摘要翻译： 射频（RF）信号可以产生具有响应于频率参考（FREF）时钟的RF频率。 电感电容（LC）振荡电路可以产生RF信号。 对于FREF时钟的第一边缘，数字到时间转换器（DTC）电路可以在具有第一延迟的基线模式中以及在FREF时钟的后续边沿处以引入第二延迟的延迟模式 值到FREF时钟。 控制器电路可以响应于FREF时钟的第一边缘而使LC-槽振荡器电路能够设置或增加作为RF信号的频率的函数的延迟模式的第二延迟值。 相位检测器电路可以检测FREF时钟的后续边沿FREF时钟和RF信号之间的相位差。

    Voltage controlled oscillator runaway prevention
    69.
    发明授权
    Voltage controlled oscillator runaway prevention 有权
    电压控制振荡器防范

    公开(公告)号：US09571109B2

    公开(公告)日：2017-02-14

    申请号：US14671259

    申请日：2015-03-27

    申请人： International Business Machines Corporation

    发明人： David M. Friend ,  James D. Strom ,  Alan P. Wagstaff

    IPC分类号： H03L7/06 ,  H03L7/085 ,  H03L7/099 ,  H03L3/00 ,  H03B5/06 ,  H03L7/18 ,  H03L7/22 ,  H03L7/14 ,  H03L7/10

    CPC分类号： H03L7/085 ,  H03B5/06 ,  H03K23/42 ,  H03L3/00 ,  H03L7/07 ,  H03L7/099 ,  H03L7/10 ,  H03L7/14 ,  H03L7/18 ,  H03L7/22 ,  H03L7/23

    摘要： A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

    摘要翻译： 用于防止锁相环（PLL）电路中的压控振荡器（VCO）失控的反馈模块可以包括第一，第二和第三输入端，以从PLL电路接收第一输出信号，参考信号和 第一控制信号。 反馈模块还可以包括用于产生第二控制信号的反馈电路，第二控制信号耦合到PLL电路的输入端，其中反馈电路通过比较第一输出信号的周期数来产生第二控制信号 到第一阈值，以及参考信号的周期数到第二阈值。