Abstract:
An imaging apparatus has an imaging area formed by arranging a plurality of imaging blocks each including a pixel array, a plurality of vertical signal lines, a horizontal output line commonly provided for the plurality of vertical signal lines to read out signals read out to the plurality of vertical signal lines, a first scanning circuit, and a second scanning circuit, wherein signals of the pixels of a selected row in the pixel array are read out to the plurality of vertical signal lines in accordance with a driving pulse from the first scanning circuit, the signals read out to the plurality of vertical signal lines are sequentially read out to the horizontal output line in accordance with a driving pulse from the second scanning circuit, and a length in a row direction of the pixel array is smaller than a length in a column direction of the pixel array.
Abstract:
An example image sensor includes a plurality of pixels arranged in an array of columns and rows, a row driver, and a control logic circuit. The row driver is coupled to pixels in a row of the array to provide a variable driving voltage to drive transistors included in the pixels of the row. The control logic circuit is coupled to provide one or more control logic signals to the row driver. The row driver adjusts a magnitude of the driving voltage in response to the one or more control logic signals.
Abstract:
A data conversion/output device includes a number of sensors, voltage-time conversion circuits that are arranged adjacent to respective sensors and change output levels upon the lapse of times corresponding to output voltage values from the sensors after a conversion operation start point in order to convert for voltage outputs of the sensors into times. The device also includes sensed data generation circuits outputting, as digital data, lapse times until the output levels of the voltage-time conversion circuits change after a conversion start point. The sensed data generation circuits include a counter for counting a clock signal. An operation start of the voltage-time conversion circuits and a start of count operation of the counter are staggered.
Abstract:
An image sensor includes a pixel array and a calibration circuit. The pixel array includes a plurality of pixels each of which includes a photoelectric conversion device configured to absorb incident light and generate a photocharge, a transfer transistor configured to transfer the photocharge from the photoelectric conversion device to a floating diffusion node, and a reset transistor configured to reset the floating diffusion node. The calibration circuit is connected to the reset transistor of each pixel, and is configured to apply a different voltage to each pixel and adjust an amount of photocharge generated by the photoelectric conversion device in each pixel.
Abstract:
An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.
Abstract:
An apparatus of one aspect includes an array of pixels. Each of the pixels includes a photosensitive element and a transfer transistor coupled with the photosensitive element. Each of the transfer transistors has a transfer gate. The apparatus also includes a first transfer gate off voltage supply conductor and a second transfer gate off voltage supply conductor. A circuit is coupled with the first and second transfer gate off voltage supply conductors. The circuit is operable to couple the first transfer gate off voltage supply conductor to transfer gates of a first subset of the pixels of the array. The circuit is also operable to concurrently couple the second transfer gate off voltage supply conductor to transfer gates of a second subset of the pixels of the array.
Abstract:
A circuit for resetting and reading out a pixel cell of a CMOS image sensor is proposed. The circuit allows for reading out the pixel cell at least two times during a main integration interval, thereby generating at least two pixel signals. The circuit further comprises means for combining the at least two pixel signals to an output signal. The means for combining are operable to combine the at least two pixel signals weighted in dependence on a saturation level of the pixel cell. A method for controlling the circuit for reading out the image sensor is also proposed.
Abstract:
In a first reset period, electrons on a floating node shared by conversion elements are reset by a sequence of reset voltages before electrons in the first conversion element are transferred to the floating node for common use. In a second reset period, electrons on the floating node are reset by a first reset voltage after the electrons in the first photoelectric conversion element are transferred to the floating node and before electrons in the second photoelectric conversion element are transferred to the floating node. The first and the second reset periods are different in length. The first reset period includes a sub-period in which resetting is performed by a highest reset voltage of the plurality of reset voltages, and the second reset period includes a sub-period in which resetting is performed by the first reset voltage, wherein these two sub-periods are substantially equal in length.
Abstract:
An imaging apparatus has an imaging area formed by arranging a plurality of imaging blocks each including a pixel array, a plurality of vertical signal lines, a horizontal output line commonly provided for the plurality of vertical signal lines to read out signals read out to the plurality of vertical signal lines, a first scanning circuit, and a second scanning circuit, wherein signals of the pixels of a selected row in the pixel array are read out to the plurality of vertical signal lines in accordance with a driving pulse from the first scanning circuit, the signals read out to the plurality of vertical signal lines are sequentially read out to the horizontal output line in accordance with a driving pulse from the second scanning circuit, and a length in a row direction of the pixel array is smaller than a length in a column direction of the pixel array.
Abstract:
A solid-state imaging device includes: a sensor unit; a vertical scanning unit and a horizontal scanning unit; column amplifier units provided at respective vertical signal lines corresponding to columns in the sensor unit and amplifying signal charges read out to the vertical signal lines; a bias current adjustment unit controlling current flowing in the vertical signal lines by changing bias current of the column amplifier units; a signal processing unit processing signal charges read out to the vertical signal lines and amplified at the column amplifier units into image signals to be outputted; an output unit to which signals outputted from the signal processing unit are supplied; a drive signal generation unit supplying drive signals to the vertical scanning unit, the horizontal scanning unit, the signal processing unit and the output unit; and an input unit supplying plural drive mode signals to the drive signal generation unit.