公开(公告)号：US4049979A

公开(公告)日：1977-09-20

申请号：US717428

申请日：1976-08-24

申请人： Mark S. D. Shieu ,  Robert B. Johnson ,  Ronald C. Laugesen

发明人： Mark S. D. Shieu ,  Robert B. Johnson ,  Ronald C. Laugesen

IPC分类号： H03K5/02 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K17/10 ,  H03K4/58 ,  H03K17/28 ,  H03K19/40

CPC分类号： H03K19/018507 ,  H03K19/01714 ,  H03K19/09425 ,  H03K5/023

摘要： Plural bootstrap capacitors are coupled to an output stage of a MOSFET driver. A conventional bootstrap driver is preceded by one or more additional bootstrap stages. Each one includes a capacitor, a tri state inverter and a delay section. When the output stage is off all capacitors are discharged. To turn the output stage on, all capacitors, including the output gate capacitance, are charged in parallel. Then each capacitor in turn is caused to pump its charge into the gate of the output stage, with the last capacitor pumping the output stage gate voltage to a level well in excess of the applied power supply voltage.

摘要翻译： 多个自举电容器耦合到MOSFET驱动器的输出级。 传统的引导驱动程序之前是一个或多个额外的引导阶段。 每个包括电容器，三态反相器和延迟部分。 当输出级关闭时，所有电容都放电。 为了打开输出级，所有电容器（包括输出栅极电容）都是并联的。 然后使每个电容器依次将其电荷泵送到输出级的栅极，最后一个电容器将输出级栅极电压泵浦到超过所施加的电源电压的电平。

公开(公告)号：US4032795A

公开(公告)日：1977-06-28

申请号：US676722

申请日：1976-04-14

申请人： Robert R. Hale

发明人： Robert R. Hale

IPC分类号： H03K19/0185 ,  H03K19/08 ,  H03K19/40

CPC分类号： H03K19/01855 ,  H03K19/018585

摘要： A circuit of complementary field effect devices whose logical input threshold voltage can be varied between levels suitable for TTL logic or CMOS or PMOS or other logic under control of an electrical signal in real time.

公开(公告)号：US4016434A

公开(公告)日：1977-04-05

申请号：US610202

申请日：1975-09-04

申请人： Robert Joseph DeFilippi

发明人： Robert Joseph DeFilippi

IPC分类号： H03F1/30 ,  H01L21/8236 ,  H01L27/088 ,  H03K3/011 ,  H03K17/14 ,  H03K17/687 ,  H03K19/0944 ,  H03L1/00 ,  H03K1/02 ,  H03K1/10 ,  H03K19/08 ,  H03K19/40

CPC分类号： H03K17/145 ,  H03K3/011 ,  H03L1/00

摘要： An FET load gate compensator circuit is disclosed which compensates for variations in the parameters characterizing the silicon substrate in FET large scale integrated circuit device, by generating a compensatory load gate voltage to be applied to the load gates of the functional circuits therein.

摘要翻译： 公开了一种FET负载栅补偿器电路，其通过产生施加到其中的功能电路的负载栅极的补偿性负载栅极电压来补偿表征FET大规模集成电路器件中的硅衬底的参数的变化。

公开(公告)号：US4013896A

公开(公告)日：1977-03-22

申请号：US622611

申请日：1975-10-15

申请人： Jean-Edgar Picquendar ,  Pham Ngu Tung

发明人： Jean-Edgar Picquendar ,  Pham Ngu Tung

IPC分类号： H03K19/08 ,  H03K3/2893 ,  H03K3/352 ,  H03K3/3565 ,  H03K19/082 ,  H03K19/34 ,  H03K19/40

CPC分类号： H03K3/352 ,  H03K19/082 ,  H03K3/2893 ,  H03K3/3565

摘要： A novel high-speed logic gate of compact design, having low energy consumption comprises a plurality of components each constituted by two complementary transistors and saturable resistors integrated upon one in the same substrate. The base of the first transistor has for its base a portion of the collector of a second transistor, and for its collector the base of the second transistor. The second transistor has its base diffused into its emitter into its base.

公开(公告)号：US4000429A

公开(公告)日：1976-12-28

申请号：US574874

申请日：1975-05-06

申请人： Kenji Yoshida ,  Kazunori Oouchi

发明人： Kenji Yoshida ,  Kazunori Oouchi

IPC分类号： G11C11/417 ,  G11C11/405 ,  G11C11/407 ,  G11C11/4094 ,  H03K5/02 ,  H03K5/04 ,  H03K17/60 ,  G11C11/40 ,  H03K19/08 ,  H03K19/40

CPC分类号： G11C11/4094 ,  G11C11/405 ,  H03K5/023

摘要： A semiconductor circuit device comprises a first depletion type n-channel insulated gate field effect transistor (hereinafter referred to as IG-FET) having its gate and source electrodes connected to each other, a second depletion type n-channel IG-FET connected between the source electrode of the first n-channel IG-FET and a positive power source and having its source and gate electrodes connected to each other, an enhancement type n-channel IG-FET connected between the source electrode of the first IG-FET and ground and having its gate electrode connected to an input terminal, an output terminal connected to the drain electrode of the first IG-FET, and a capacitor connected to the above-mentioned output terminal and ground. When a potential on the above-mentioned input terminal is dropped down to zero volt, the first depletion type IG-FET is abruptly shifted to the ON state, causing the capacitor to be abruptly charged by a positive power source. When the potential on the above-mentioned input terminal is raised to a predetermined positive level, the capacitor is slowly discharged through a zero-volt channel i.e. a remaining channel of the first depletion type IG-FET whose gate electrode is biased to zero volt.

摘要翻译： 一种半导体电路器件包括其栅极和源极彼此连接的第一耗尽型n沟道绝缘栅场效应晶体管（以下称为IG-FET），第二耗尽型n沟道IG-FET连接在 第一n沟道IG-FET的源电极和正电源并且其源电极和栅电极彼此连接，连接在第一IG-FET的源电极和地之间的增强型n沟道IG-FET 并且其栅电极连接到输入端，连接到第一IG-FET的漏电极的输出端和连接到上述输出端并接地的电容器。 当上述输入端子上的电位下降到零伏特时，第一耗尽型IG-FET突然偏移到导通状态，使得电容器被正电源突然充电。 当上述输入端子上的电位上升到预定的正电平时，电容器通过零伏通道缓慢放电，即第一个耗尽型IG-FET的剩余通道，栅极被偏压到零伏特。

公开(公告)号：US3962589A

公开(公告)日：1976-06-08

申请号：US548189

申请日：1975-02-10

申请人： Ury Priel ,  Robert A. Anselmo

发明人： Ury Priel ,  Robert A. Anselmo

IPC分类号： H03K19/088 ,  H03K19/40

CPC分类号： H03K19/088

摘要： A dual inverter circuit wherein the first inverter circuit includes a pair of phase splitter transistors, one serving to feed the base of the pull-up transistor in the first inverter circuit and the other serving to feed the base of the phase splitter transistor in the second inverter circuit. The circuit provides a minimum delay time between the operation of the first inverter and the turn-on time of the second inverter while also providing active pull-up circuits, i.e., pull-up transistors, in the two inverters to insure fast operate times for both inverters especially desirable when feeding into large capacitance loads.

摘要翻译： 一种双反相器电路，其中第一反相器电路包括一对分相晶体管，一对用于馈送第一反相器电路中的上拉晶体管的基极，另一个用于在第二反相器晶体管的基极中馈送第二 逆变电路。 该电路在第一反相器的操作和第二反相器的导通时间之间提供最小延迟时间，同时在两个反相器中还提供有源上拉电路，即上拉晶体管，以确保快速操作时间 当馈入大电容负载时，两个逆变器特别理想。

公开(公告)号：US3953743A

公开(公告)日：1976-04-27

申请号：US553637

申请日：1975-02-27

申请人： Richard James Hollingsworth

发明人： Richard James Hollingsworth

IPC分类号： H03K19/0944 ,  H03K19/08 ,  H03K19/22 ,  H03K19/36 ,  H03K19/40

CPC分类号： H03K19/09441

摘要： A circuit for generating a logic function and its logical complement of N binary variables utilizing MOS transistors which are all of the same conductivity type. The circuit may include an N input NAND gate comprising N MOS transistors and a load element, the conduction paths of the transistors connected in series with the load element to form a first series circuit and an inverter circuit having N+1 MOS transistors, the conduction paths of which are connected in series to form a second series circuit. Each series circuit is connected between the same operating voltage terminals and the two are interconnected to one another in such manner that the power dissipation of the circuit compares favorably with a CMOS inverter.

摘要翻译： 用于产生逻辑功能的电路及其利用所有相同导电类型的MOS晶体管的N个二进制变量的逻辑补码。 电路可以包括N个输入NAND门，其包括N个MOS晶体管和一个负载元件，晶体管的导通路径与负载元件串联以形成第一串联电路和具有N + 1个MOS晶体管的反相器电路，该导通 其路径串联连接以形成第二串联电路。 每个串联电路连接在相同的工作电压端子之间，并且两个相互连接，使得该电路的功率损耗与CMOS反相器相当。

公开(公告)号：US3937983A

公开(公告)日：1976-02-10

申请号：US564855

申请日：1975-04-03

申请人： John A. Reed

发明人： John A. Reed

IPC分类号： H03K19/017 ,  H03K19/0185 ,  H03K19/08 ,  H03K17/10 ,  H03K19/40

CPC分类号： H03K19/01714 ,  H03K19/018507

摘要： An MOS dynamic buffer circuit described in terms of an inverter and used for inverting a timing signal is disclosed. Through the use of bootstrapping, the output from the inverter is equal to the voltage used to drive the inverter without having conduction through the output transistor when the inverter is not supplying an output signal. Thus, the inverter does not require the large amounts of standby power associated with prior art circuits.

摘要翻译： 公开了一种根据逆变器描述并用于反转定时信号的MOS动态缓冲电路。 通过使用自举，当逆变器不提供输出信号时，逆变器的输出等于用于驱动逆变器的电压，而不会通过输出晶体管导通。 因此，逆变器不需要与现有技术电路相关联的大量待机功率。

公开(公告)号：US3916217A

公开(公告)日：1975-10-28

申请号：US45806174

申请日：1974-04-04

申请人： HITACHI LTD

发明人： SHIMADA SHUNJI ,  HATSUKANO YOSHIKAZU

IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/096 ,  H03K19/173 ,  H03K19/08 ,  H03K5/13 ,  H03K19/30 ,  H03K19/40

CPC分类号： H03K19/018557 ,  H03K19/0963 ,  H03K19/173

摘要： An integrated logical circuit device for providing a wired ''''OR'''' logic function between chips or circuit devices which include logical circuits of the ratioless type, comprises ''''floating'''' circuits and OR gate circuits which are formed within the corresponding chips or circuit devices. Each floating circuit determines the level of an output signal in dependence on a signal from the logical circuit at a prescribed time and makes its output terminal floating at another time. The OR gate circuits receive the output signal at the prescribed time and a signal from the logical circuit at the another time, to provide a wired OR circuit.

摘要翻译： 一种集成逻辑电路装置，用于在包括无竞争类型的逻辑电路的芯片或电路装置之间提供有线“或”逻辑功能，包括形成在相应芯片或电路装置内的“浮动”电路和“或”门电路。 每个浮动电路根据来自逻辑电路的信号在规定时间确定输出信号的电平，并使其输出端在另一时间浮置。 OR门电路在规定时间接收输出信号，并在另一时间接收来自逻辑电路的信号，以提供有线OR电路。

公开(公告)号：US3903431A

公开(公告)日：1975-09-02

申请号：US42932473

申请日：1973-12-28

申请人： TELETYPE CORP

发明人： HEEREN RICHARD H

IPC分类号： H03K19/017 ,  H03K19/096 ,  H03K19/08 ,  H03K5/13 ,  H03K17/60 ,  H03K19/40

CPC分类号： H03K19/096 ,  H03K19/01728

摘要： A clock driven dynamic inverter produces high speed-low power signal inversion, with a high voltage output swing. Such operation is accomplished in one illustrative dynamic inverter embodiment with two specially phased clock driven switching MOSFETs, a dynamically driven load MOSFET, incorporating positive capacitive voltage feedback, and an input signal-responsive driver MOSFET.

摘要翻译： 时钟驱动的动态逆变器产生高速低功率信号反相，具有高电压输出摆幅。 这种操作在一个说明性的动态逆变器实施例中实现，其具有两个特别相位的时钟驱动开关MOSFET，包含正电容电压反馈的动态驱动负载MOSFET和输入信号响应驱动器MOSFET。