公开(公告)号：US20180315751A1

公开(公告)日：2018-11-01

申请号：US15632877

申请日：2017-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  G06F17/50

CPC classification number: H01L27/088 ,  G06F17/5072 ,  H01L21/76895 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L2027/11866

Abstract: A system and method for creating a layout for a vertical gate all around standard cell are described. Metal gate is placed all around two vertical nanowire sheets formed on a silicon substrate. A gate contact is formed on the metal gate between the two vertical nanowire sheets. Gate extension metal (GEM) is placed above the metal gate at least on the gate contact. A via for a gate is formed at a location on the GEM where a local interconnect layer is available to be used for routing a gate connection. Local metal layers are placed for connecting local routes and power connections.

公开(公告)号：US20180314652A1

公开(公告)日：2018-11-01

申请号：US15965256

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jonathan Lawrence Campbell ,  Yuping Shen

IPC: G06F13/12 ,  G06F13/40 ,  G06F1/16 ,  G06F1/32

CPC classification number: G06F13/126 ,  G06F1/1632 ,  G06F1/3293 ,  G06F13/4081

Abstract: Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes determining a docking state of a dockable device while at least an application is running. Application migration from the dockable device to a docking station is initiated when the dockable device is moving to a docked state. Application migration from the docking station to the dockable device is initiated when the dockable device is moving to an undocked state. The application continues to run during the application migration from the dockable device to the docking station or during the application migration from the docking station to the dockable device.

公开(公告)号：US10114761B2

公开(公告)日：2018-10-30

申请号：US15442462

申请日：2017-02-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Wade K. Smith ,  Kostantinos Danny Christidis

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1009 ,  G06F9/38 ,  G06F13/00 ,  G06F13/28

Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available. The fact that finite state machines are reserved to particular quality-of-service levels means that if all such finite state machines for a particular quality-of-service level are used by pending translation requests, then the translation lookaside buffer does not accept more translation requests for that quality-of-service level.

公开(公告)号：US20180307603A1

公开(公告)日：2018-10-25

申请号：US15497162

申请日：2017-04-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Shuai Che

IPC: G06F12/0811 ,  G06F9/50 ,  G06F12/0846

CPC classification number: G06F12/0811 ,  G06F9/5083 ,  G06F12/0848 ,  G06F2212/00

Abstract: Improvements to traditional schemes for storing data for processing tasks and for executing those processing tasks are disclosed. A set of data for which processing tasks are to be executed is processed through a hierarchy to distribute the data through various elements of a computer system. Levels of the hierarchy represent different types of memory or storage elements. Higher levels represent coarser portions of memory or storage elements and lower levels represent finer portions of memory or storage elements. Data proceeds through the hierarchy as “tasks” at different levels. Tasks at non-leaf nodes comprise tasks to subdivide data for storage in the finer granularity memories or storage units associated with a lower hierarchy level. Tasks at leaf nodes comprise processing work, such as a portion of a calculation. Two techniques for organizing the tasks in the hierarchy presented herein include a queue-based technique and a graph-based technique.

公开(公告)号：US20180302105A1

公开(公告)日：2018-10-18

申请号：US15489438

申请日：2017-04-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Shrikanth Ganapathy ,  Steven Raasch

IPC: H03M13/11 ,  H03M13/00 ,  G11C16/08 ,  G11C11/56

CPC classification number: G06F11/1064 ,  G11C29/42 ,  H03M13/19

Abstract: A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.

公开(公告)号：US10095637B2

公开(公告)日：2018-10-09

申请号：US15267094

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory W. Smaus ,  John M. King ,  Michael D. Achenbach ,  Kevin M. Lepak ,  Matthew A. Rafacz ,  Noah Bamford

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/14 ,  G06F9/52 ,  G06F9/30

Abstract: Techniques for improving execution of a lock instruction are provided herein. A lock instruction and younger instructions are allowed to speculatively retire prior to the store portion of the lock instruction committing its value to memory. These instructions thus do not have to wait for the lock instruction to complete before retiring. In the event that the processor detects a violation of the atomic or fencing properties of the lock instruction prior to committing the value of the lock instruction, the processor rolls back state and executes the lock instruction in a slow mode in which younger instructions are not allowed to retire until the stored value of the lock instruction is committed. Speculative retirement of these instructions results in increased processing speed, as instructions no longer need to wait to retire after execution of a lock instruction.

公开(公告)号：US20180277624A1

公开(公告)日：2018-09-27

申请号：US15466643

申请日：2017-03-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L21/32134 ,  H01L21/32136 ,  H01L23/5223 ,  H01L28/75 ,  H01L28/84 ,  H01L28/90

Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer on top of an oxide layer which is on top of a metal layer. The process etches trenches into areas of the polysilicon layer where the repeated trenches determine a frequency of an oscillating wave structure to be formed later. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the polysilicon layer both on areas with the trenches and on areas without the trenches. A series of a barrier metal and a second polysilicon layer is deposited on the oscillating structure. The process completes the MIM capacitor with metal nodes contacting each of the top metal and the bottom metal of the oscillating structure.

公开(公告)号：US10078882B2

公开(公告)日：2018-09-18

申请号：US15346395

申请日：2016-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Philip J. Rogers ,  David Gotwalt ,  Tom Frisinger ,  Rex McCrary

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/4818 ,  G06F9/4881 ,  G06F9/5044 ,  G06F2209/5021 ,  G06F2209/509

Abstract: A method of processing commands is provided. The method includes holding commands in queues and executing the commands in an order based on their respective priority. Commands having the same priority are held in the same queue.

公开(公告)号：US10067718B2

公开(公告)日：2018-09-04

申请号：US15274178

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Glennis Eliagh Covington ,  Kevin M. Brandl ,  Nienchi Hu ,  Shannon T. Kesner

IPC: G06F12/00 ,  G06F3/06

Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.

公开(公告)号：US20180247388A1

公开(公告)日：2018-08-30

申请号：US15442383

申请日：2017-02-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Chan ,  Christopher J. Brennan

IPC: G06T1/60 ,  H04N19/176 ,  H04L9/08

CPC classification number: G06T1/60 ,  H04L9/0861 ,  H04N19/176 ,  H04N19/70

Abstract: Systems, apparatuses, and methods for compressing pixel data are disclosed. In one embodiment, if a block of pixel data is equal to a constant value, a processor compresses the block down to a metadata value which specifies the constant value for the entire block of pixel data. The processor also detects if the constant value is equal to a video specific typical minimum or maximum value. In another embodiment, the processor receives a plurality of M-bit pixel components which are most significant bit aligned in N-bit containers. Next, the processor shifts the M-bit pixel components down into least significant bit locations of the N-bit containers. Then, the processor converts the N-bit containers into M-bit containers. Next, the processor compresses the M-bit containers to create a compressed block of pixel data which is then stored in a memory subsystem.