Abstract:
A method and apparatus for conserving power in a wireless communication device. The method includes receiving at least a portion of a PHY protocol data unit (PPDU) frame, where the PPDU frame includes an aggregate MAC protocol data unit (A-MPDU) field. The method also includes comparing a receiver address (RA) within the A-MPDU field to a stored address of the wireless communication device and, if the received RA does not match the stored address, causing power to be removed from one or more circuits of the wireless communication device for a calculated period of time.
Abstract:
A method and apparatus for negotiating an idle subchannel set for a wireless data transmission. The method includes transmitting an indication of a first set of idle subchannels to a wireless station. The method also includes receiving an indication of a second set of idle subchannels from the wireless station. The method further includes determining a final set of idle subchannels based on the indication of the first set of idle subchannels and the indication of the second set of idle subchannels.
Abstract:
A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
Abstract:
An adaptive uniform polishing system is equipped with feedback control to apply localized adjustments during a polishing operation. The adaptive uniform polishing system disclosed has particular application to the semiconductor industry. Such an adaptive uniform polishing system includes a rotatable head that holds a semiconductor wafer, and a processing unit structured to be placed in contact with an exposed surface of the wafer. The processing unit includes a rotatable macro-pad and a plurality of rotatable micro-pads that can polish different portions of the exposed surface at different rotation speeds and pressures. Thus, uniformity across the exposed surface can be enhanced by applying customized treatments to different areas. Customized treatments can include the use of different pad materials and geometries. Parameters of the adaptive uniform polishing system are programmable, based on in-situ data or data from other operations in a fabrication process, using advanced process control.
Abstract:
A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.
Abstract:
Embodiments of the present disclosure are directed to leadframe packages with wettable sides and methods of manufacturing same. In one embodiment, the leads of the leadframe packages have recesses with a curved profile formed therein. The recesses are plated with a solder wettable layer of conductive material that enables solder to flow along the surface during surface mounting of the package to a board, such as a PCB.
Abstract:
A method for providing a priority-based, low-collision distributed coordination function in a wireless network that includes a plurality of stations is provided. The method includes determining a priority for a first station and selecting a back-off time for the first station based on the priority.
Abstract:
Disclosed herein is a microfluidic pumping device having a piezoelectric member positioned above a displaceable membrane. A voltage is applied across the piezoelectric member causing the piezoelectric member to displace the membrane. Displacement of the membrane increases and decreases pressure in a cavity that is below the membrane. The increases and decreases in pressure actuate cantilevered check valve members to facilitate unidirectional liquid flow through the pumping device.
Abstract:
Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
Abstract:
A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.