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    Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element formed over a bottom conductor and methods of forming the same
    71.
    发明授权
    Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element formed over a bottom conductor and methods of forming the same 有权
    使用在底部导体上形成的选择性制造的碳纳米管可逆电阻切换元件的记忆单元及其形成方法

    公开(公告)号：US08530318B2

    公开(公告)日：2013-09-10

    申请号：US12410789

    申请日：2009-03-25

    申请人： April D. Schricker

    发明人： April D. Schricker

    IPC分类号： H01L21/8222

    CPC分类号： H01L27/101 ,  B82Y10/00 ,  G11C13/025 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1616 ,  H01L51/0048 ,  H01L51/0575

    摘要： In some aspects, a method of fabricating a memory cell is provided that includes: (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (“CNT”) material above the first conductor by: (a) fabricating a CNT seeding layer on the first conductor, wherein the CNT seeding layer comprises silicon-germanium (“Si/Ge”), (b) planarizing a surface of the deposited CNT seeding layer, and (c) selectively fabricating CNT material on the CNT seeding layer; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided.

    摘要翻译： 在一些方面，提供一种制造存储单元的方法，其包括：（1）在衬底之上制造第一导体; （2）通过以下步骤选择性地制造第一导体上方的碳纳米管（“CNT”）材料：（a）在第一导体上制造CNT籽晶层，其中CNT籽晶层包括硅 - 锗（“Si / Ge” ），（b）平坦化沉积的CNT籽晶层的表面，和（c）在CNT籽晶层上选择性地制造CNT材料; （3）在CNT材料之上制造二极管; 和（4）在二极管上方制造第二导体。 提供了许多其他方面。

    Flexible multi-pulse set operation for phase-change memories
    75.
    发明授权
    Flexible multi-pulse set operation for phase-change memories 有权
    用于相变存储器的灵活多脉冲设置操作

    公开(公告)号：US08379437B2

    公开(公告)日：2013-02-19

    申请号：US12551553

    申请日：2009-08-31

    申请人： Tyler Thorp ,  Roy E. Scheuerlein

    发明人： Tyler Thorp ,  Roy E. Scheuerlein

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0092

    摘要： Methods and apparatus are provided that include reading a plurality of sets of program pulse tuning instructions from a memory page, the memory page including a plurality of memory cells; and creating a plurality of program pulses in accordance with the plurality of sets of program pulses to program the plurality of memory cells. The plurality of sets of program pulse tuning instructions may be different from one another in at least one respect.

    摘要翻译： 提供了包括从存储器页面读取多组编程脉冲调整指令的方法和装置，所述存储器页面包括多个存储器单元; 以及根据所述多组编程脉冲创建多个编程脉冲，以对所述多个存储单元进行编程。 多组编程脉冲调谐指令在至少一个方面可以彼此不同。

    Methods and apparatus for supporting substrates
    76.
    发明授权
    Methods and apparatus for supporting substrates 有权
    用于支撑基材的方法和装置

    公开(公告)号：US08365682B2

    公开(公告)日：2013-02-05

    申请号：US11140777

    申请日：2005-05-31

    申请人： Wendell T. Blonigan ,  Carl Sorensen ,  John M. White ,  Robin L. Tiner

    发明人： Wendell T. Blonigan ,  Carl Sorensen ,  John M. White ,  Robin L. Tiner

    IPC分类号： B65G49/07

    CPC分类号： H01L21/67259 ,  H01L21/68742 ,  H01L21/68778

    摘要： Substrate support methods and apparatus include vertically aligned lift pins that have bearing surfaces that engage friction plates and/or magnetic fields to maintain the vertical orientation of the lift pins during substrate lifting. In some embodiments, a magnetic field and/or weighting may alternatively or additionally be used to control the vertical orientation of the lift pins, limit the angle of the lift pins, and/or prevent the lift pins from unintentionally binding in a susceptor as the susceptor is raised and prevent the resulting uneven support of the substrate.

    摘要翻译： 衬底支撑方法和装置包括垂直对齐的提升销，其具有接合摩擦板和/或磁场的承载表面，以在衬垫提升期间保持提升销的垂直取向。 在一些实施例中，可以替代地或另外地使用磁场和/或加权来控制提升销的垂直定向，限制提升销的角度和/或防止提升销在基座中无意地结合，因为 感受器被升高并且防止由此产生的基板不均匀的支撑。

    Methods and apparatus for monitoring and encouraging health and fitness
    78.
    发明授权
    Methods and apparatus for monitoring and encouraging health and fitness 有权
    监测和鼓励健康和健身的方法和设备

    公开(公告)号：US08337367B2

    公开(公告)日：2012-12-25

    申请号：US13305714

    申请日：2011-11-28

    申请人： Brian M. Dugan

    发明人： Brian M. Dugan

    IPC分类号： A63B71/00

    CPC分类号： A61B5/486 ,  A61B5/0022 ,  A61B5/1112 ,  A61B5/4866 ,  A61B5/6824 ,  A61B5/6831 ,  A61B5/6898 ,  A61B5/7475 ,  A61B2503/12 ,  A63B24/0062 ,  A63B2024/0068 ,  G06F19/00 ,  G06F19/3418 ,  G06F19/3475 ,  G06F19/3481 ,  G06F19/36 ,  G06Q10/087 ,  G06Q30/0621 ,  G06Q30/0623 ,  G06Q30/0631 ,  G06Q30/0633 ,  G09B5/00 ,  G09B5/02 ,  G09B19/0092 ,  G16H20/30 ,  G16H20/60 ,  G16H30/20 ,  G16H40/67

    摘要： Methods and apparatus are provided for monitoring and encouraging health and fitness. In accordance with a first aspect, an apparatus is provided that is adapted to assist in weight loss and exercise. The apparatus comprises a personal digital assistant (PDA) having computer program code adapted to assist in at least one of calorie counting, meal selection, meal suggestion, weight monitoring, weight loss or gain monitoring, fat consumption monitoring, sugar consumption monitoring and salt consumption monitoring. The PDA also includes computer program code adapted to display historical data regarding at least one of calorie counting, meal selection, meal suggestion, weight monitoring, weight loss or gain monitoring, fat consumption monitoring, sugar consumption monitoring and salt consumption monitoring. Numerous other embodiments are provided, as are methods, systems and computer program products.

    摘要翻译： 提供了监测和鼓励健康和健身的方法和设备。 根据第一方面，提供一种适于辅助减肥和锻炼的装置。 该装置包括具有计算机程序代码的个人数字助理（PDA），其适于帮助卡路里计数，膳食选择，膳食建议，体重监测，体重减轻或增益监测，脂肪消耗监测，糖消耗监测和盐消耗中的至少一种 监控。 PDA还包括适于显示关于卡路里计数，膳食选择，膳食建议，体重监测，减肥或增益监测，脂肪消耗监测，糖消耗监测和盐消耗监测中的至少一种的历史数据的计算机程序代码。 提供了许多其他实施例，方法，系统和计算机程序产品也是如此。

    Optimization of critical dimensions and pitch of patterned features in and above a substrate
    79.
    发明授权
    Optimization of critical dimensions and pitch of patterned features in and above a substrate 有权
    优化衬底中和图案上的图案特征的临界尺寸和间距

    公开(公告)号：US08283706B2

    公开(公告)日：2012-10-09

    申请号：US12136766

    申请日：2008-06-10

    申请人： James M. Cleeves ,  Roy E. Scheuerlein

    发明人： James M. Cleeves ,  Roy E. Scheuerlein

    IPC分类号： H01L29/80

    CPC分类号： H01L27/105 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.

    摘要翻译： 在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。 本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。 存储器阵列的一个级别包括例如平行轨道和扇出区域。 希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。 这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在 轨道，并且在不太关键的扇出区域更放松。

    Resist feature and removable spacer pitch doubling patterning method for pillar structures
    80.
    发明授权
    Resist feature and removable spacer pitch doubling patterning method for pillar structures 有权
    支柱结构的抗蚀特征和可移除的间隔物间距倍增图案化方法

    公开(公告)号：US08084347B2

    公开(公告)日：2011-12-27

    申请号：US12318609

    申请日：2008-12-31

    申请人： Yung-Tin Chen ,  Steven J. Radigan

    发明人： Yung-Tin Chen ,  Steven J. Radigan

    IPC分类号： H01L21/44

    CPC分类号： H01L45/1691 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/1021

    摘要： A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming sidewall spacers on the at least two features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one layer using the first feature, the filler feature and the second feature as a mask.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成至少一个层，在所述至少一个层上形成可成像材料的至少两个间隔的特征，在所述至少两个特征上形成侧壁间隔物，并填充第一 第一特征上的侧壁间隔物和具有填充物特征的第二特征上的第二侧壁间隔物。 该方法还包括选择性地去除侧壁间隔物以留下第一特征，填料特征和第二特征彼此间隔开，并且使用第一特征，填充物特征和第二特征作为掩模蚀刻至少一个层 。