公开(公告)号：US20210050437A1

公开(公告)日：2021-02-18

申请号：US17086688

申请日：2020-11-02

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG

IPC分类号： H01L29/778 ,  H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285 ,  H01L29/66

摘要： Embodiments of the present application disclose a semiconductor structure and a manufacturing method for the semiconductor structure, which solve problems of complicated manufacturing process and poor stability and reliability of existing semiconductor structures. The semiconductor structure includes: a substrate; a channel layer and a barrier layer sequentially superimposed on the substrate, wherein the channel layer and the barrier layer are made of GaN-based materials and an upper surface of the barrier layer is Ga-face; and a p-type GaN-based semiconductor layer formed in a gate region of the barrier layer. An upper surface of the p-type GaN-based semiconductor layer is N-face.

公开(公告)号：US20200350162A1

公开(公告)日：2020-11-05

申请号：US16931612

申请日：2020-07-17

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG

IPC分类号： H01L21/02 ,  H01L29/06

摘要： A semiconductor structure includes a substrate; a nucleation layer located above the substrate; and a metal nitride thin film located between the nucleation layer and the substrate. A diffusion of atoms in a material of the substrate is suppressed by depositing the metal nitride thin film between the substrate and the nucleation layer, so that a thickness of the nucleation layer is significantly reduced, and a total thermal resistance of the semiconductor structure is reduced.

公开(公告)号：US20190311914A1

公开(公告)日：2019-10-10

申请号：US16441586

申请日：2019-06-14

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG

IPC分类号： H01L21/324 ,  H01L21/02 ,  H01L29/778 ,  H01L29/207 ,  H01L29/66

摘要： A method for preparing a p-type semiconductor layer, an enhanced device and a method for manufacturing the same disclosed relate to the technical field of microelectronics. The method for preparing a p-type semiconductor layer includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.

公开(公告)号：US20190035845A1

公开(公告)日：2019-01-31

申请号：US16148989

申请日：2018-10-01

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Liyang ZHANG ,  Kai CHENG

IPC分类号： H01L27/15 ,  H01L33/14 ,  H01L33/38 ,  H01L33/44 ,  H01L33/46 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L33/06 ,  H01L33/00

摘要： A semiconductor light-emitting device comprises: an insulating base, a current diffusion layer, light-emitting structure layers and an insulating layer. The current diffusion layer includes: a first electrode connecting part, a second electrode connecting part, N contact parts and N+1 flat parts. N+1 light-emitting structure layers are correspondingly disposed on the N+1 flat parts, and each of the N+1 light-emitting structure layers includes: a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked on a corresponding flat part. N grooves are formed on a side of the second semiconductor layer away from the active layer, depth of the N grooves is less than the thickness of the second semiconductor layer, and the N contact parts correspond to the N grooves.

公开(公告)号：US10026834B2

公开(公告)日：2018-07-17

申请号：US15190690

申请日：2016-06-23

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai Cheng

IPC分类号： H01L29/205 ,  H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20

摘要： A method of manufacturing an enhanced device and an enhance device are provided. The method comprises: preparing a substrate, and forming a non-planar structure in the substrate; depositing a nitride channel layer on the substrate, a gate region, a source region and a drain region being defined on the nitride channel layer, the gate region of the nitride channel layer having a non-planar structure transferred from the non-planar structure of the substrate; depositing a nitride barrier layer on the nitride channel layer, the nitride barrier layer having a non-planar structure located above and corresponding to the non-planar structure of the nitride channel layer, the nitride barrier layer and the nitride channel layer forming a nitride channel layer/nitride barrier layer heterojunction.

公开(公告)号：US09640624B2

公开(公告)日：2017-05-02

申请号：US14896364

申请日：2014-01-06

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai Cheng

IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/868 ,  H01L29/872 ,  H01L29/20 ,  H01L21/283 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/861 ,  H01L29/41 ,  H01L21/768

CPC分类号： H01L29/402 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/76804 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41 ,  H01L29/417 ,  H01L29/41725 ,  H01L29/42352 ,  H01L29/42356 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66462 ,  H01L29/66681 ,  H01L29/7787 ,  H01L29/7823 ,  H01L29/8611 ,  H01L29/868 ,  H01L29/872

摘要： A semiconductor device comprises: a semiconductor device active region; an electrode shape controlling layer disposed on the semiconductor device active region, the electrode shape controlling layer containing aluminum, the content of aluminum being changed in a direction from bottom to up from the semiconductor device active region, an electrode region being disposed on the electrode shape controlling layer, a groove extended toward the semiconductor device active region and penetrating through the electrode shape controlling layer longitudinally being disposed in the electrode region, all or part of a side surface of the groove having a shape corresponding to the content of aluminum in the electrode shape controlling layer; and an electrode disposed in the groove in the electrode region entirely or partially, the electrode having a shape matching with the shape of the groove, a bottom portion of the electrode being contacted with the semiconductor device active region.

公开(公告)号：US20160233328A1

公开(公告)日：2016-08-11

申请号：US15099649

申请日：2016-04-15

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG

IPC分类号： H01L29/778 ,  H01L23/31 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

摘要： An III group nitride semiconductor device comprises: a substrate; a nitride semiconductor layer located on the substrate; a passivation layer located on the nitride semiconductor layer, a portion of the passivation layer in a gate region being etched to expose the nitride semiconductor layer so as to form a gate groove; a composite dielectric layer located on the passivation layer and the gate groove, the composite dielectric layer comprising one or more combination structures of two or more of a nitride dielectric layer, an oxynitride dielectric layer and an oxide dielectric layer which are formed sequentially in the direction away from the substrate; and a source electrode and a drain electrode respectively located in a source region and a drain region on the nitride semiconductor layer, and a gate electrode located in a gate region between the source region and the drain region on the composite dielectric layer.

摘要翻译： III族氮化物半导体器件包括：衬底; 位于所述基板上的氮化物半导体层; 位于所述氮化物半导体层上的钝化层，蚀刻栅极区域中的所述钝化层的一部分以暴露所述氮化物半导体层以形成栅极沟槽; 位于所述钝化层和所述栅极沟槽上的复合介电层，所述复合介电层包括沿所述方向依次形成的氮化物电介质层，氧氮化物电介质层和氧化物电介质层中的两个或更多个的一个或多个组合结构 远离基材; 以及分别位于氮化物半导体层上的源极区域和漏极区域中的源极电极和漏极电极，以及位于复合介电层上的源极区域和漏极区域之间的栅极区域中的栅极电极。

公开(公告)号：US20160126325A1

公开(公告)日：2016-05-05

申请号：US14896364

申请日：2014-01-06

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/872 ,  H01L29/861 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/283 ,  H01L21/31 ,  H01L29/417 ,  H01L29/778 ,  H01L29/66

CPC分类号： H01L29/402 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/76804 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41 ,  H01L29/417 ,  H01L29/41725 ,  H01L29/42352 ,  H01L29/42356 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66462 ,  H01L29/66681 ,  H01L29/7787 ,  H01L29/7823 ,  H01L29/8611 ,  H01L29/868 ,  H01L29/872

摘要： A semiconductor device comprises: a semiconductor device active region; an electrode shape controlling layer disposed on the semiconductor device active region, the electrode shape controlling layer containing aluminum, the content of aluminum being changed in a direction from bottom to up from the semiconductor device active region, an electrode region being disposed on the electrode shape controlling layer, a groove extended toward the semiconductor device active region and penetrating through the electrode shape controlling layer longitudinally being disposed in the electrode region, all or part of a side surface of the groove having a shape corresponding to the content of aluminum in the electrode shape controlling layer; and an electrode disposed in the groove in the electrode region entirely or partially, the electrode having a shape matching with the shape of the groove, a bottom portion of the electrode being contacted with the semiconductor device active region.

摘要翻译： 半导体器件包括：半导体器件有源区; 设置在所述半导体器件有源区上的电极形状控制层，所述电极形状控制层含有铝，所述铝的含量从所述半导体器件有源区域向下向上变化，电极区域设置在所述电极形状 控制层，朝向半导体器件有源区延伸并且纵向穿过电极形状控制层的沟槽设置在电极区域中，槽的侧表面的全部或一部分具有与电极中的铝含量相对应的形状 形状控制层; 以及电极，其全部或部分设置在所述电极区域的所述槽内，所述电极具有与所述槽的形状相匹配的形状，所述电极的底部与所述半导体器件活性区域接触。

公开(公告)号：US20150187925A1

公开(公告)日：2015-07-02

申请号：US14143736

申请日：2013-12-30

申请人： Enkris Semiconductor, Inc.

发明人： Kai Cheng

IPC分类号： H01L29/778 ,  H01L29/205 ,  H01L29/201 ,  H01L29/423 ,  H01L29/20 ,  H01L29/51

CPC分类号： H01L29/7786 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7789

摘要： An enhancement-mode device is provided. A spontaneous polarization effect and a piezoelectric effect in a crystal of nitride are greatest in a direction and do not exist or are minimal in a non-polar and a semi-polar direction, which is used to form the enhancement-mode device. A groove having a non-polar surface or a semi-polar surface is formed in an epitaxial multilayer structure, thereby interrupting two-dimensional electron gas in the groove. When a gate voltage is increased, the electron density on the non-polar and semi-polar surfaces in the groove is increased consequently, thereby realizing an enhancement-mode operation.

摘要翻译： 提供增强型设备。 氮化物晶体中的自发极化效应和压电效应在<0002>方向上最大，并且在非极性和半极性方向上不存在或最小，用于形成增强型器件 。 在外延层叠结构中形成具有非极性表面或半极性表面的槽，从而中断槽内的二维电子气。 当栅极电压增加时，沟槽中非极性和半极性表面上的电子密度增加，从而实现增强模式操作。

公开(公告)号：US20150187885A1

公开(公告)日：2015-07-02

申请号：US14143628

申请日：2013-12-30

申请人： Enkris Semiconductor, Inc.

发明人： Kai Cheng

IPC分类号： H01L29/20 ,  H01L33/06 ,  H01L33/32 ,  H01L31/18 ,  H01L31/0304 ,  H01L21/02 ,  H01L29/201 ,  H01L29/205 ,  H01L29/15 ,  H01L29/778 ,  H01L29/66 ,  H01L33/00 ,  H01L31/0352

CPC分类号： H01L29/2003 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/7786 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32

摘要： A semiconductor epitaxial structure is provided, which includes: a nitride nucleation layer, formed on a substrate including silicon, sapphire, patterned sapphire substrate (PSS) or silicon carbide, a nitride layer on the nitride nucleation layer and an multi-layer structure in the nitride layer. The multi-layer structure includes a first intermediate layer and a second intermediate layer formed on the first intermediate layer. The first intermediate layer includes AlGaN, the second intermediate layer includes AlGaN or aluminium nitride, and the average composition of Al in the first intermediate layer is less than that in the second intermediate layer. A method for forming a semiconductor epitaxial structure is provided. The semiconductor epitaxial structure according to the present disclosure can not decrease the crystalline quality when a compressive stress is introduced, which may avoid a crack phenomenon or quality degradation caused by the change of temperature.

摘要翻译： 提供了一种半导体外延结构，其包括：形成在包括硅，蓝宝石，图案化蓝宝石衬底（PSS）或碳化硅）的衬底上的氮化物成核层，氮化物成核层上的氮化物层和 氮化物层。 多层结构包括形成在第一中间层上的第一中间层和第二中间层。 第一中间层包括AlGaN，第二中间层包括AlGaN或氮化铝，并且第一中间层中的Al的平均组成小于第二中间层中的Al的平均组成。 提供了一种形成半导体外延结构的方法。 根据本公开的半导体外延结构在引入压缩应力时不能降低结晶质量，这可以避免由温度变化引起的裂纹现象或质量劣化。