公开(公告)号：US20140143887A1

公开(公告)日：2014-05-22

申请号：US14086591

申请日：2013-11-21

申请人： Fairchild Semiconductor Corporation

发明人： Bert Marston ,  John R. Turner ,  Michael Smith ,  Kenneth P. Snowdon ,  Nathan Charland

IPC分类号： G06F21/62

CPC分类号： G06F21/62 ,  G06F12/1441 ,  G06F21/86 ,  G06F2212/202 ,  G06F2221/2143 ,  G06F2221/2147

摘要： This document discusses, among other things, security measures for shielding or protecting data or sensitive signals on an integrated circuit (IC). The systems and methods disclosed herein can allow erasing sensitive data when access is not locked, locking out access to sensitive data during normal operations through both indirect and direct means, and shielding sensitive signals from invasive probing or manipulation.

摘要翻译： 本文件还讨论了在集成电路（IC）上屏蔽或保护数据或敏感信号的安全措施。 本文公开的系统和方法可以允许当访问未被锁定时擦除敏感数据，通过间接和直接手段在正常操作期间锁定对敏感数据的访问，并且屏蔽敏感信号以防侵入探测或操纵。

公开(公告)号：US20140132312A1

公开(公告)日：2014-05-15

申请号：US14081442

申请日：2013-11-15

申请人： Fairchild Semiconductor Corporation

发明人： Laszlo Balogh

IPC分类号： H03K17/06

CPC分类号： H03K17/06

摘要： Driver circuitry and methods are provided for driving a semiconductor device. The driver circuitry includes a buck converter configured to generate a baseline current, and a capacitor coupled between an output of the buck converter and ground, the capacitor configured to store charge during an off-state of the buck converter and to discharge the stored charge as a peak current during an on-state of the buck converter, wherein the baseline current reaches a current limit prior to the capacitor being fully discharged, and an output current at an output of the buck converter is based, at least in part, on the baseline current and the peak current.

摘要翻译： 为驱动半导体器件提供驱动电路和方法。 驱动器电路包括被配置为产生基线电流的降压转换器和耦合在降压转换器和地的输出之间的电容器，该电容器被配置为在降压转换器的截止状态期间存储电荷并且将所存储的电荷作为 在降压转换器的导通状态期间的峰值电流，其中基线电流在电容器完全放电之前达到电流限制，并且降压转换器的输出处的输出电流至少部分地基于 基线电流和峰值电流。

公开(公告)号：US20140117968A1

公开(公告)日：2014-05-01

申请号：US14061177

申请日：2013-10-23

申请人： Fairchild Semiconductor Corporation

发明人： Tyler Daigle

IPC分类号： G05F3/02

CPC分类号： G05F3/267 ,  G05F3/02 ,  G05F3/242 ,  G05F3/247 ,  G05F3/26 ,  G05F3/262 ,  G05F3/30

摘要： This application discusses apparatus and methods for reducing supply voltage induced band gap voltage variation. In an example, a method of compensating a reference voltage current source for supply voltage variation can include providing at least a portion if a reference current for establishing the reference voltage using a first output transistor coupled to the supply voltage, maintaining a constant voltage across the first output transistor using a second output transistor coupled between the first output transistor and an output node, modulating a compensation impedance between a first node and ground as the supply voltage varies, the first node located where the first output transistor is coupled to the second output transistor, and wherein the modulating includes modulating the compensation impedance to substantially equal an output impedance, the output impedance measured between an output node and an input for the supply voltage.

摘要翻译： 本应用讨论了降低电源电压感应带隙电压变化的装置和方法。 在一个示例中，用于补偿用于电源电压变化的参考电压电流源的方法可以包括：提供至少一部分，如果用于使用耦合到电源电压的第一输出晶体管建立参考电压的参考电流，保持恒定电压 第一输出晶体管，其使用耦合在第一输出晶体管和输出节点之间的第二输出晶体管，在电源电压变化时调制第一节点与地之间的补偿阻抗，位于第一输出晶体管耦合到第二输出端的第一节点 晶体管，并且其中所述调制包括将所述补偿阻抗调制为基本上等于输出阻抗，所述输出阻抗在输出节点和所述电源电压的输入之间测量的输出阻抗。

公开(公告)号：US20140115344A1

公开(公告)日：2014-04-24

申请号：US14057245

申请日：2013-10-18

申请人： Fairchild Semiconductor Corporation

发明人： Erik Maier ,  John R. Turner

IPC分类号： G06F13/40 ,  G06F21/60

CPC分类号： G06F13/40 ,  G06F21/602 ,  H04L1/1692 ,  H04L2001/0094

摘要： This application discusses, among other things, communication apparatus and methods, and more particularly, a single conductor or single wire communication scheme. In an example, a method for communicating between a master device and a slave device using a first single conductor can include transmitting a first ping on the first single conductor using a master device, the first single conductor configured to couple the master device to a slave device, receiving a slave ping on the first single conductor at the master device during a ping interval, toggling a logic level of the first single conductor prior to sending a first data packet using pulses having a duration of less than one half of a unit interval, such as a unit interval associated with a bit interval.

摘要翻译： 本申请尤其涉及通信装置和方法，尤其涉及单导体或单线通信方案。 在一个示例中，用于使用第一单个导体在主设备和从设备之间通信的方法可以包括使用主设备在第一单个导体上发送第一个ping，第一单个导体被配置为将主设备耦合到从设备 在ping间隔期间在主设备处的第一单个导体上接收从设备ping，在使用具有小于单位间隔的一半的持续时间的脉冲发送第一数据分组之前切换第一单个导体的逻辑电平 ，例如与位间隔相关联的单位间隔。

公开(公告)号：US20140103428A1

公开(公告)日：2014-04-17

申请号：US14141340

申请日：2013-12-26

申请人： Fairchild Semiconductor Corporation

发明人： Suku Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802

摘要： Methods for fabricating MOSFET devices with superjunction having high breakdown voltages (>600 volts) with competitively low specific resistance include growing an epitaxial layer of a second conductivity type on a substrate of a first conductivity type, forming a trench in the epitaxial layer, and growing a second epitaxial layer along the sidewalls and bottom of the trench. The second epitaxial layer is doped with a dopant of first conductivity type. MOSFET devices with superjunction having high breakdown voltages include a first epitaxial layer of a second conductivity type disposed over a substrate of a first conductivity type and a trench formed in the epitaxial layer. The trench includes a second epitaxial layer grown along the sidewalls and bottom of the trench.

摘要翻译： 用于制造具有高击穿电压（> 600伏特）的具有竞争力低电阻率的MOSFET的MOSFET器件的方法包括在第一导电类型的衬底上生长第二导电类型的外延层，在外延层中形成沟槽，并且生长 沿沟槽的侧壁和底部的第二外延层。 第二外延层掺杂有第一导电类型的掺杂剂。 具有高击穿电压的MOSFET的MOSFET器件包括设置在第一导电类型的衬底上的第二导电类型的第一外延层和形成在外延层中的沟槽。 沟槽包括沿沟槽的侧壁和底部生长的第二外延层。

公开(公告)号：US20140098297A1

公开(公告)日：2014-04-10

申请号：US14103013

申请日：2013-12-11

申请人： Fairchild Semiconductor Corporation

发明人： Julie Lynn Stultz ,  Steven Macaluso ,  Enrique O. Rodriguez

IPC分类号： H03K17/16

CPC分类号： H03K17/16 ,  H03K17/005 ,  H03K17/30 ,  Y10T307/76

摘要： A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

摘要翻译： 开关可以被配置为在第一输入处接收第一信号，并且根据开关的状态在输出端提供输出信号。 可以延迟开关状态改变，直到接收到与当前开关状态不同的请求开关状态的指示，并且第一信号达到阈值。

公开(公告)号：US20140085064A1

公开(公告)日：2014-03-27

申请号：US13930096

申请日：2013-06-28

申请人： Fairchild Semiconductor Corporation

发明人： Philip J. Crawley ,  Majid Shushtarian

IPC分类号： G08B6/00

CPC分类号： G08B6/00 ,  B06B1/0246

摘要： This document discusses, among other things, apparatus and methods for controlling a haptic transducer. In an example, a haptic controller can include an active termination driver having a configurable output impedance. The active termination driver can be configured to drive a haptic transducer and to process back electro-magnetic force (EMF) of the haptic transducer to provide motion feedback of the haptic transducer. In an example, the haptic controller can include a processor to provide a command signal to the active termination driver and to determine a resonant frequency of the haptic device using the motion feedback of the haptic transducer.

摘要翻译： 本文件尤其讨论了用于控制触觉换能器的装置和方法。 在一个示例中，触觉控制器可以包括具有可配置输出阻抗的有源终端驱动器。 活动终止驱动器可以被配置为驱动触觉换能器并且处理触觉换能器的电磁力（EMF），以提供触觉换能器的运动反馈。 在一个示例中，触觉控制器可以包括处理器，以向主动终端驱动器提供命令信号，并且使用触觉换能器的运动反馈来确定触觉装置的谐振频率。

公开(公告)号：US20140070392A1

公开(公告)日：2014-03-13

申请号：US14026181

申请日：2013-09-13

申请人： Fairchild Semiconductor Corporation

发明人： Chung-Lin Wu ,  Steven Sapp ,  Bigildis Dosdos ,  Suresh Belani ,  Sunggeun Yoon

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/495 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/84

摘要： A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.

摘要翻译： 第一实施例是公共漏极+夹具20.其底表面上具有传统的漏极接触，并且是倒装芯片安装在半蚀刻引线框架40上，半导体引线框架40具有连接到源极，门和公共端的外部源极，栅极和漏极触点 管芯20的漏极。公共漏极夹50将漏极30连接到相对的栅极触点之间的外部触点。 第二实施例是直接排水实施例+热塞。 器件80具有顶部漏极接触36，其跨越管芯的底部延伸到公共漏极30，其倒装芯片安装到具有连接到源极的外部源极，栅极和漏极触点的栅极和公共漏极的半蚀刻引线框架 的模具80。

公开(公告)号：US20140070329A1

公开(公告)日：2014-03-13

申请号：US14020782

申请日：2013-09-06

申请人： Fairchild Semiconductor Corporation

发明人： Allan Tungul Flores ,  Romel N. Manatad ,  Jan Vincent C. Mancelita

IPC分类号： H01L27/088 ,  H01L23/52 ,  H01L21/56

CPC分类号： H01L27/088 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/52 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/16245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/73255 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012

摘要： A wireless multichip module has a leadframe structure 10 with potions for receiving flip-chip mounted dies, including an integrated circuit 20 and high and low side mosfets 30, 40 to form a half-bridge circuit encapsulated in molding compound 70. The module is assembled without any bond wires. The module may also carry passive components including an external input capacitor 150 or an internal input capacitor 350.

摘要翻译： 无线多芯片模块具有引线框结构10，其具有用于接收倒装芯片安装的管芯的引导框架结构10，其包括集成电路20以及高低侧的mosfet 30,40，以形成封装在模制复合物70中的半桥电路。该模块被组装 没有任何接线。 该模块还可以承载包括外部输入电容器150或内部输入电容器350的无源元件。

公开(公告)号：US20140062440A1

公开(公告)日：2014-03-06

申请号：US14018847

申请日：2013-09-05

申请人： Fairchild Semiconductor Corporation

发明人： James Garrett

IPC分类号： H02M3/156

CPC分类号： H02M3/156 ,  G01R19/0092 ,  H02M2001/0009 ,  H02M2001/0045

摘要： A device and method for sensing an inductor current in an inductor is provided that generates a voltage signal proportionate to the inductor current if the inductor is connected to a positive supply and simulates the inductor current if the inductor is not connected to the positive supply. The voltage signal may be generated by sampling an input voltage from the inductor onto a capacitor if the inductor is connected to the positive supply. The inductor current may be simulated by generating a simulation current and pushing the simulation current onto the capacitor.

摘要翻译： 提供了用于感测电感器中的电感器电流的装置和方法，其产生与电感器电流成比例的电压信号，如果电感器连接到正电源并且如果电感器未连接到正电源则模拟电感器电流。 如果电感器连接到正电源，则可以通过将来自电感器的输入电压采样到电容器上来产生电压信号。 可以通过产生模拟电流并将模拟电流推到电容器上来模拟电感器电流。