公开(公告)号：US20140054691A1

公开(公告)日：2014-02-27

申请号：US14068781

申请日：2013-10-31

申请人： Fairchild Semiconductor Corporation

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US09379045B2

公开(公告)日：2016-06-28

申请号：US14026181

申请日：2013-09-13

申请人： Fairchild Semiconductor Corporation

发明人： Chung-Lin Wu ,  Steven Sapp ,  Bigildis Dosdos ,  Suresh Belani ,  Sunggeun Yoon

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/433 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/495 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/84

摘要： A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.

摘要翻译： 第一实施例是公共漏极+夹具20.其底表面上具有传统的漏极接触，并且是倒装芯片安装在半蚀刻引线框架40上，半导体引线框架40具有连接到源极，门和公共端的外部源极，栅极和漏极触点 管芯20的漏极。公共漏极夹50将漏极30连接到相对的栅极触点之间的外部触点。 第二实施例是直接排水实施例+热塞。 器件80具有顶部漏极接触36，其跨越管芯的底部延伸到公共漏极30，其倒装芯片安装到具有连接到源极的外部源极，栅极和漏极触点的栅极和公共漏极的半蚀刻引线框架 的模具80。

公开(公告)号：US08592895B2

公开(公告)日：2013-11-26

申请号：US13633038

申请日：2012-10-01

申请人： Fairchild Semiconductor Corporation

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US08742401B2

公开(公告)日：2014-06-03

申请号：US14068781

申请日：2013-10-31

申请人： Fairchild Semiconductor Corporation

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US20130181282A1

公开(公告)日：2013-07-18

申请号：US13633038

申请日：2012-10-01

申请人： Fairchild Semiconductor Corporation

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US20140070392A1

公开(公告)日：2014-03-13

申请号：US14026181

申请日：2013-09-13

申请人： Fairchild Semiconductor Corporation

发明人： Chung-Lin Wu ,  Steven Sapp ,  Bigildis Dosdos ,  Suresh Belani ,  Sunggeun Yoon

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/495 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/84

摘要： A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.

摘要翻译： 第一实施例是公共漏极+夹具20.其底表面上具有传统的漏极接触，并且是倒装芯片安装在半蚀刻引线框架40上，半导体引线框架40具有连接到源极，门和公共端的外部源极，栅极和漏极触点 管芯20的漏极。公共漏极夹50将漏极30连接到相对的栅极触点之间的外部触点。 第二实施例是直接排水实施例+热塞。 器件80具有顶部漏极接触36，其跨越管芯的底部延伸到公共漏极30，其倒装芯片安装到具有连接到源极的外部源极，栅极和漏极触点的栅极和公共漏极的半蚀刻引线框架 的模具80。

公开(公告)号：US08866218B2

公开(公告)日：2014-10-21

申请号：US13918562

申请日：2013-06-14

申请人： Fairchild Semiconductor Corporation

发明人： Daniel M. Kinzer ,  Steven Sapp ,  Chung-Lin Wu ,  Oseob Jeon ,  Bigidis Dosdos

IPC分类号： H01L29/66 ,  H01L23/62 ,  H01L23/02 ,  H01L29/78 ,  H01L29/417 ,  H01L23/00

CPC分类号： H01L29/7827 ,  H01L24/13 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： In one general aspect, a system can include a through-silicon-via (TSV) coupling a drain region associated with a vertical transistor to a back metal disposed on a second side of the substrate opposite the first side. The system can include a first metal layer, and a second metal layer aligned orthogonal to the first metal layer. The system can define a conduction path extending substantially vertically through the TSV to the substrate and laterally through the substrate.

摘要翻译： 在一个一般方面，系统可以包括将与垂直晶体管相关联的漏极区域与布置在与第一侧相对的衬底的第二侧上的背面金属耦合的穿硅通孔（TSV）。 该系统可以包括第一金属层和与第一金属层正交排列的第二金属层。 该系统可以限定通过TSV基本垂直延伸到衬底并横向穿过衬底的导电路径。

公开(公告)号：US20140203355A1

公开(公告)日：2014-07-24

申请号：US14223351

申请日：2014-03-24

申请人： Fairchild Semiconductor Corporation

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

摘要翻译： 根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。 该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。 源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。 该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。 导体层可与半导体区形成肖特基接触。