公开(公告)号：US06566240B2

公开(公告)日：2003-05-20

申请号：US09957609

申请日：2001-09-21

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L2144

CPC classification number: H01L23/3735 ,  H01L21/84 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

公开(公告)号：US06445054B1

公开(公告)日：2002-09-03

申请号：US09636353

申请日：2000-08-10

Applicant: Tatjana Traijkovic ,  Florin Udrea ,  Gehan Anil Joseph Amaratunga

Inventor： Tatjana Traijkovic ,  Florin Udrea ,  Gehan Anil Joseph Amaratunga

IPC: H01L2358

CPC classification number: H01L29/0619 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/7397 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprises an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device. The edge portion comprises a substrate region (12) of a first semiconductor type. The voltage termination structure comprises at least one first termination region (11) of a second semiconductor type, the or each first termination region having at least one of either second and third termination regions (11a, 11b) of third and fourth semiconductor types located at substantially opposing edges thereof. The second and third termination regions (11a, 11b) respectively have a higher semiconductor doping concentration than the edge portion substrate region (12) and a lower semiconductor doping concentration than the first termination region(s) (11).

Abstract translation: 一种半导体器件包括具有电压终端结构的有源区，位于器件的边缘部分附近与有源区相邻。 边缘部分包括第一半导体类型的衬底区域（12）。 电压端接结构包括至少一个第二半导体类型的第一端接区域（11），该或每个第一端接区域具有第三和第四半导体类型的第二和第三端接区域（11a，11b）中的至少一个位于 基本相对的边缘。 第二和第三端接区域（11a，11b）分别具有比边缘部分衬底区域（12）更高的半导体掺杂浓度和比第一端接区域（11）更低的半导体掺杂浓度。

公开(公告)号：US08866252B2

公开(公告)日：2014-10-21

申请号：US13233672

申请日：2011-09-15

Applicant: Tanya Trajkovic ,  Florin Udrea ,  Vasantha Pathirana ,  Nishad Udugampola

Inventor： Tanya Trajkovic ,  Florin Udrea ,  Vasantha Pathirana ,  Nishad Udugampola

IPC: H01L23/58 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer.

Abstract translation: 我们描述了具有p顶层的n-漂移区的RESURF半导体器件，并且其中在该p顶层中形成该器件的MOS（金属氧化物半导体）沟道。

公开(公告)号：US20130320511A1

公开(公告)日：2013-12-05

申请号：US13486614

申请日：2012-06-01

Applicant: Elizabeth Kho Ching Tee ,  Alexander Dietrich Hölke ,  Steven John Pilkington ,  Deb Kumar Pal ,  Marina Antoniou ,  Florin Udrea

Inventor： Elizabeth Kho Ching Tee ,  Alexander Dietrich Hölke ,  Steven John Pilkington ,  Deb Kumar Pal ,  Marina Antoniou ,  Florin Udrea

IPC: H01L29/02

CPC classification number: H01L29/402 ,  H01L21/761 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/7823 ,  H01L29/861

Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure.

Abstract translation: 一种包括p或p +掺杂部分和通过半导体漂移部分从p或p +掺杂部分分离的n或n +掺杂部分的半导体器件。 该装置还包括邻近漂移部分设置的至少一个终端部分。 所述至少一个终端部分包括超结结构。

公开(公告)号：US08482031B2

公开(公告)日：2013-07-09

申请号：US12648818

申请日：2009-12-29

Applicant: Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

Inventor： Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

IPC: H01L29/739 ,  H01L21/761 ,  H01L21/331

CPC classification number: H01L29/7394 ,  H01L29/66325 ,  H01L29/7393

Abstract: This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain αv for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT αv

Abstract translation: 本发明一般涉及横向绝缘栅双极晶体管（LIGBT），例如在集成电路中，提高LIGBT的开关速度的方法，抑制体硅LIGBT中的寄生晶闸管闩锁的方法以及制造LIGBT的方法 。 特别地，抑制体硅LIGBT中的寄生晶闸管闩锁的方法包括为LIGBT的寄生晶闸管的垂直晶体管选择电流增益α，使得在LIGBT的至少一个预定操作模式中，alphav <1 其中alphap是具有由半导体表面和富含金属的环氧树脂裸片附着之间的肖特基接触形成的基极 - 发射极的寄生双极晶体管的电流增益。

公开(公告)号：US08053783B2

公开(公告)日：2011-11-08

申请号：US11575114

申请日：2005-09-08

Applicant: Gehan Anil Joseph Amaratunga ,  Mihai Brezeanu ,  Jeremy Suhail Rashid ,  Nalin Lalith Rupesinghe ,  Antonella Tajani ,  Daniel James Twitchen ,  Florin Udrea ,  Christopher John Howard Wort

Inventor： Gehan Anil Joseph Amaratunga ,  Mihai Brezeanu ,  Jeremy Suhail Rashid ,  Nalin Lalith Rupesinghe ,  Antonella Tajani ,  Daniel James Twitchen ,  Florin Udrea ,  Christopher John Howard Wort

IPC: H01L31/10 ,  H01J47/00

CPC classification number: H01L31/108 ,  H01L31/028 ,  H01L31/0288 ,  H01L31/118 ,  Y02E10/547

Abstract: A high voltage diamond based switching device capable of sustaining high currents in the on state with a relatively low impedance and a relatively low optical switching flux, and capable of being switched off in the presence of the high voltage being switched. The device includes a diamond body having a Schottky barrier contact, held in reverse bias by the applied voltage to be switched, to an essentially intrinsic diamond layer or portion in the diamond body, a second metal contact, and an optical source or other illuminating or irradiating device such that when the depletion region formed by the Schottky contact to the intrinsic diamond layer is exposed to its radiation charge carriers are generated. Cain in the total number of charge carriers then occurs as a result of these charge carriers accelerating under the field within the intrinsic diamond layer and generating further carriers by assisted avalanche breakdown.

Abstract translation: 一种高电压金刚石开关器件，能够以较低阻抗和相对低的光开关通量在导通状态下维持高电流，并且能够在存在正在切换的高电压的情况下被关断。 该装置包括具有肖特基势垒接触件的金刚石体，通过施加的被切换的电压以相反的偏置保持在金刚石本体中的基本上本征的金刚石层或部分，第二金属接触和光源或其它照明或 照射装置，使得当通过与本征金刚石层的肖特基接触形成的耗尽区域暴露于其辐射电荷载体时。 因此，由于这些电荷载流子在本征金刚石层内的场下加速并且通过辅助的雪崩击穿而产生另外的载流子，所以导致电荷载流子总数的隐藏。

公开(公告)号：US20110227151A1

公开(公告)日：2011-09-22

申请号：US12724771

申请日：2010-03-16

Applicant: Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

Inventor： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

IPC: H01L27/06

CPC classification number: H01L29/407 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/404 ,  H01L29/66143 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate and a second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover a portion of the termination structure oxide layer.

Abstract translation: 为功率晶体管提供端接结构。 端接结构包括具有有源区和端接区的半导体衬底。 衬底具有第一类导电性。 终端沟槽位于终端区域中并且从有源区域的边界朝向半导体衬底的边缘延伸。 具有第二类型的导电性的掺杂区域设置在终端沟槽下方的衬底中。 在与边界相邻的侧壁上形成MOS栅极。 掺杂区域从与栅极间隔开的部分MOS栅极向半导体衬底的边缘延伸。 端接结构氧化物层形成在覆盖MOS栅极的一部分并朝向衬底边缘延伸的端接沟槽上。 第一导电层形成在半导体衬底的背侧表面上，并且第二导电层形成在有源区顶部，MOS栅极的暴露部分之上，并延伸以覆盖端接结构氧化物层的一部分。

公开(公告)号：US20110156096A1

公开(公告)日：2011-06-30

申请号：US12648847

申请日：2009-12-29

Applicant: Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

Inventor： Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7394 ,  H01L29/402

Abstract: This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1×1017/cm3; a lateral drift region of a second, opposite conductivity type adjacent the substrate region and electrically coupled to said substrate region; a charge injection region of the first conductivity type to inject charge toward said lateral drift region; a gate to control flow of said charge in said lateral drift region; metal enriched adhesive below said substrate region; and an intermediate layer below said substrate region to substantially suppress charge injection into said substrate region from said metal enriched adhesive.

Abstract translation: 本发明一般涉及LIGBT，包含LIGBT的IC和形成LIGBT的方法，更具体地涉及包含第一导电类型的衬底区域和小于约1×1017 / cm3的峰值掺杂剂浓度的LIGBT; 邻近所述衬底区域的第二相反导电类型的横向漂移区域，并电耦合到所述衬底区域; 第一导电类型的电荷注入区域，用于向所述横向漂移区域注入电荷; 用于控制所述横向漂移区域中的所述电荷的流动的门; 在所述衬底区域下面的富含金属的粘合剂; 以及在所述衬底区域下面的中间层，以基本上抑制从所述金属富集粘合剂向所述衬底区域注入电荷。

公开(公告)号：US20110057230A1

公开(公告)日：2011-03-10

申请号：US12648818

申请日：2009-12-29

Applicant: Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

Inventor： Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

IPC: H01L29/739 ,  H01L21/761 ,  H01L21/331

CPC classification number: H01L29/7394 ,  H01L29/66325 ,  H01L29/7393

Abstract: This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain αv for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT αv

Abstract translation: 本发明一般涉及横向绝缘栅双极晶体管（LIGBT），例如在集成电路中，提高LIGBT的开关速度的方法，抑制体硅LIGBT中的寄生晶闸管闩锁的方法以及制造LIGBT的方法 。 特别地，抑制体硅LIGBT中的寄生晶闸管闩锁的方法包括为LIGBT的寄生晶闸管的垂直晶体管选择电流增益αv，使得在LIGBT的至少一个预定操作模式中，αv<1 -αp，其中αp是具有由半导体表面和富含金属的环氧树脂芯片之间的肖特基接触形成的基极 - 发射极结的寄生双极晶体管的电流增益。

公开(公告)号：US20100242592A1

公开(公告)日：2010-09-30

申请号：US12739520

申请日：2008-10-24

Applicant: Ibraheem Haneef ,  Howard P. Hodson ,  Robert Miller ,  Florin Udrea

Inventor： Ibraheem Haneef ,  Howard P. Hodson ,  Robert Miller ,  Florin Udrea

IPC: G01F1/692 ,  C03C15/00

CPC classification number: G01F1/6845 ,  G01F1/7084 ,  G01N3/24 ,  G01N2203/0226 ,  G01N2203/0623

Abstract: This invention relates to hot film shear stress sensors and their fabrication. We describe a hot film shear stress sensor comprising a silicon substrate supporting a membrane having a cavity underneath, said membrane bearing a film of metal and having electrical contacts for heating said film, and wherein said membrane comprises a silicon oxide membrane, where in said metal comprises aluminium or tungsten, and wherein said membrane has a protective layer of a silicon-based material over said film of metal. In preferred embodiments the sensor is fabricated by a CMOS process and the metal comprises aluminium or tungsten.

Abstract translation: 本发明涉及热膜剪切应力传感器及其制造。 我们描述了一种热膜剪切应力传感器，其包括支撑具有下面空腔的膜的硅衬底，所述膜承载金属膜并具有用于加热所述膜的电触点，并且其中所述膜包括氧化硅膜，其中在所述金属 包括铝或钨，并且其中所述膜在所述金属膜上具有硅基材料的保护层。 在优选实施例中，传感器通过CMOS工艺制造，并且金属包括铝或钨。