公开(公告)号：US20110191526A1

公开(公告)日：2011-08-04

申请号：US12809039

申请日：2008-12-23

申请人： Brent Haukness ,  Ian Shaeffer

发明人： Brent Haukness ,  Ian Shaeffer

IPC分类号： G06F12/00

CPC分类号： G11C16/32 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C16/04 ,  G11C16/107 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/4402

摘要： This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly. A mechanism is also provided for recalibrating memory previously marked. By minimizing variability, flash memory can be applied to a broader range of designs and potentially to a broader set of main memory applications.

摘要翻译： 本公开提供了一种准确地确定与诸如设备，块或页面之类的闪速存储器细分有关的预期交易时间的方法。 通过执行测试事务来对每个这样的单元的每个位进行编程，可以预先确定每个单元的最大预期编程时间并用于调度目的。 例如，在简单的实现中，可以识别相对精确的经验测量的时间限制并用于有效地管理和调度闪速存储器事务，而不等待最终解决写入非响应页面的尝试。 本公开还提供经验测量的最大闪存交易时间的其他用途，包括经由多个存储器模式和优先存储器; 例如，如果需要高性能模式，则可以容忍闪速存储器交易时间的低变化，并且可以相对快速地标记不满足这些原理的单元。 还提供了一种用于重新校准之前标记的存储器的机制。 通过最小化可变性，闪存可以应用于更广泛的设计，并可能应用于更广泛的主存储器应用。

公开(公告)号：US20110066792A1

公开(公告)日：2011-03-17

申请号：US12812745

申请日：2009-02-04

申请人： Ian Shaeffer ,  Brent Haukness

发明人： Ian Shaeffer ,  Brent Haukness

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C16/349 ,  G06F12/0246 ,  G06F2212/7211 ,  G11C16/3495 ,  Y02D10/13

摘要： This disclosure provides a method and system that segment flash memory to have differently managed regions. More particularly, flash memory is segmented into a “non-volatile” region, where program counts are restricted to preserve baseline retention assumptions, and a “volatile” region, where program counts are unrestricted. Contrary to conventional wisdom, wear leveling is not performed on all flash memory, as the volatile region is regarded as degraded, and as the non-volatile region has program counts restricted to promote long-term retention. More than two regions may also be created; each of these may be associated with intermediate program counts and volatility expectations, and wear leveling may be applied to each of these on an independent basis if desired. Refresh procedures may optionally be applied to the region of flash memory which is treated as volatile memory.

摘要翻译： 本公开提供了一种将闪存分段为具有不同管理区域的方法和系统。 更具体地说，闪速存储器被分割为“非易失性”区域，其中程序计数被限制以保持基线保留假设，而“易失性”区域，其中程序计数是不受限制的。 与传统智慧相反，随着挥发性区域被认为退化，并且随着非挥发性区域的程序计数被限制以促进长期保留，所有闪存都不进行磨损均衡。 还可以创建两个以上的地区; 这些可以与中间程序计数和波动期望相关联，并且如果需要，可以在独立的基础上对这些中的每一个应用磨损均衡。 刷新过程可以可选地应用于被视为易失性存储器的闪存区域。

公开(公告)号：US20110004726A1

公开(公告)日：2011-01-06

申请号：US12920564

申请日：2009-02-19

申请人： Brent S. Haukness ,  Ian Shaeffer ,  Gary B. Bronner

发明人： Brent S. Haukness ,  Ian Shaeffer ,  Gary B. Bronner

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C16/16

摘要： Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device.

摘要翻译： 描述电路的实施例。 该电路包括产生多个分段擦除命令的控制逻辑，以擦除存储在另一个电路内形成的存储器件的存储单元中的信息。 注意，在存储器件内执行多个分段擦除命令中的单个擦除命令可能不足以擦除存储在存储单元中的信息。 此外，第一电路包括从控制逻辑接收多个分段擦除命令并将多个分段擦除命令发送到存储器件的接口。

公开(公告)号：US20100180143A1

公开(公告)日：2010-07-15

申请号：US12596360

申请日：2008-04-14

申请人： Frederick A. Ware ,  Carl Werner ,  Ian Shaeffer

发明人： Frederick A. Ware ,  Carl Werner ,  Ian Shaeffer

IPC分类号： G06F1/04 ,  G11C7/00 ,  G06F12/00

CPC分类号： G11C8/18 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028

摘要： Techniques for improved timing control of memory devices are disclosed. In one embodiment, the techniques may be realized as a memory controller to communicate with a memory device via a communications link. The memory controller may comprise a memory interface to exchange data with the memory device via a set of N conductors according to at least one clock, the data being encoded such that each M bits of data are represented by at least one symbol and each symbol is associated with a combination of signal levels on a group of n conductors, wherein M

摘要翻译： 公开了用于改进存储器件定时控制的技术。 在一个实施例中，这些技术可以被实现为存储器控制器，以经由通信链路与存储器设备进行通信。 存储器控制器可以包括存储器接口，用于根据至少一个时钟经由一组N个导体与存储器件交换数据，该数据被编码，使得每个M位的数据由至少一个符号表示，并且每个符号是 与一组n导体上的信号电平的组合相关联，其中M

公开(公告)号：US20100146199A1

公开(公告)日：2010-06-10

申请号：US12703521

申请日：2010-02-10

申请人： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

发明人： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC分类号： G06F12/00 ,  G06F3/00 ,  G06F13/00

CPC分类号： G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

摘要翻译： 除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。 例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点到点链路）信号路径提供数据， 所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。 集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。 由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。 缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

公开(公告)号：US20090161453A1

公开(公告)日：2009-06-25

申请号：US12049928

申请日：2008-03-17

申请人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

发明人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC分类号： G11C7/22

CPC分类号： G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

摘要翻译： 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。 在该系统的变型中，存储器芯片上的相位检测器被配置为从存储器控制器接收包括时钟信号，标记信号和数据选通信号的信号，其中标记信号包括标记特定时钟的脉冲 在时钟信号周期。 在该变型中，相位检测器被配置为使用标记信号来在时钟信号中画出特定时钟周期，并且使用数据选通信号来捕获窗口化的时钟信号，从而产生返回到 内存控制器便于校准时序关系。

公开(公告)号：US20070235851A1

公开(公告)日：2007-10-11

申请号：US11402393

申请日：2006-04-11

申请人： Frederick Ware ,  Ely Tsern ,  Ian Shaeffer

发明人： Frederick Ware ,  Ely Tsern ,  Ian Shaeffer

IPC分类号： H01L23/02 ,  H01L23/48

CPC分类号： H01L21/768 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00

摘要： The point-to-point interconnection system for stacked devices includes a device, a substrate, operational circuitry, at least three electrical contacts and a conductor. The substrate has opposing first and second surfaces. A first electrical contact is mechanically coupled to the first surface of the device and electrically coupled to the operational circuitry. The second electrical contact is mechanically coupled to the first surface. The third electrical contact is mechanically coupled to the second surface opposite the first electrical contact. The conductor electrically couples the second electrical contact to the third electrical contact.

摘要翻译： 用于堆叠器件的点对点互连系统包括器件，衬底，操作电路，至少三个电触点和导体。 基板具有相对的第一和第二表面。 第一电触头机械耦合到器件的第一表面并电耦合到操作电路。 第二电触点机械耦合到第一表面。 第三电触头机械耦合到与第一电触头相对的第二表面。 导体将第二电触头电耦合到第三电触点。