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186 条记录 (耗时 0.021 秒)

    Memory module system with efficient control of on-die termination
    71.
    发明授权
    Memory module system with efficient control of on-die termination 有权
    内存模块系统，具有对片上终端的高效控制

    公开(公告)号：US07180327B2

    公开(公告)日：2007-02-20

    申请号：US10997406

    申请日：2004-11-24

    申请人： Byung-Se So ,  Jeong-Hyeon Cho ,  Jae-Jun Lee

    发明人： Byung-Se So ,  Jeong-Hyeon Cho ,  Jae-Jun Lee

    IPC分类号： H03K17/16 ,  G11C8/12

    CPC分类号： H04L25/0278 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1084

    摘要： For ODT (on-die termination) control within a memory module system, just one pin from the memory controller is used for sending command signals indicating an activated one of the memory devices. The activated memory device includes components that are turned on for generating the ODT control signal for controlling an ODT circuit of inactivated memory device(s). The components for generating an ODT control signal within the inactivated memory devices are turned off for minimized power consumption.

    摘要翻译： 对于存储器模块系统内的ODT（片上终端）控制，仅使用来自存储器控制器的一个引脚来发送指示已激活的存储器件的命令信号。 激活的存储器件包括被开启以产生用于控制非激活存储器件的ODT电路的ODT控制信号的组件。 用于在非激活的存储器件内产生ODT控制信号的组件被关闭以最小化功率消耗。

    Delay locked loop circuit for a synchronous semiconductor memory device and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device
    72.
    发明申请
    Delay locked loop circuit for a synchronous semiconductor memory device and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device 有权

    公开(公告)号：US20060152259A1

    公开(公告)日：2006-07-13

    申请号：US11321599

    申请日：2005-12-29

    申请人： Jae-Jun Lee ,  Hoe-Ju Chung

    发明人： Jae-Jun Lee ,  Hoe-Ju Chung

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812

    摘要： A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.

    Memory module and a method of arranging a signal line of the same
    74.
    发明申请
    Memory module and a method of arranging a signal line of the same 失效
    存储器模块及其配置信号线的方法

    公开(公告)号：US20050185439A1

    公开(公告)日：2005-08-25

    申请号：US11064671

    申请日：2005-02-24

    申请人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

    发明人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

    IPC分类号： G06F12/00 ,  G11C5/06 ,  G11C11/401 ,  H05K1/18

    CPC分类号： G11C5/063 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

    摘要： The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.

    摘要翻译： 本发明公开了一种存储模块及其配置信号线的方法。 布置存储器模块的信号线的方法包括：将多个存储器分类为包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点，并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点，以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点，接收外部信号，并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。

    High-speed memory system
    75.
    发明授权
    High-speed memory system 有权
    高速内存系统

    公开(公告)号：US06828819B2

    公开(公告)日：2004-12-07

    申请号：US10353924

    申请日：2003-01-30

    申请人： Myun-Joo Park ,  Byung-Se So ,  Jae-Jun Lee

    发明人： Myun-Joo Park ,  Byung-Se So ,  Jae-Jun Lee

    IPC分类号： H03K1716

    CPC分类号： G06F13/4086 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H05K1/023 ,  H05K1/14

    摘要： A memory system includes a chipset mounted on a circuit board, and first and second memory module connectors mounted respectively on the circuit board. The first and second memory modules are inserted into the first and second memory module connectors, respectively. The memory system further includes a bus connected to the chipset and the first and second memory module connectors so to create a branch point. Each of the first and second memory modules includes at least one memory device connected to the bus via a stub line and a stub resistor. Impedance of the bus is less than that of the stub line.

    摘要翻译： 存储器系统包括安装在电路板上的芯片组，以及分别安装在电路板上的第一和第二存储器模块连接器。 第一和第二存储器模块分别插入到第一和第二存储器模块连接器中。 存储器系统还包括连接到芯片组的总线和第一和第二存储器模块连接器，以便产生分支点。 第一和第二存储器模块中的每一个包括经由短截线和短截线电阻连接到总线的至少一个存储器件。 公交车的阻力小于短线的阻力。

    Multi-blade electric rotary razor
    76.
    发明授权
    Multi-blade electric rotary razor 有权
    多刃电动旋转剃须刀

    公开(公告)号：US09174350B2

    公开(公告)日：2015-11-03

    申请号：US13819132

    申请日：2011-08-30

    申请人： Young Ho Park ,  Jae Jun Lee

    发明人： Young Ho Park ,  Jae Jun Lee

    IPC分类号： B26B19/14 ,  B26B19/38 ,  B26B21/00 ,  B26B21/40

    CPC分类号： B26B19/145 ,  B26B19/14 ,  B26B19/3853 ,  B26B21/00 ,  B26B21/4081

    摘要： The present invention relates to a multi-blade electric rotary razor which comprises a razor blade cartridge turned by a motor, and at least one pair of razor blade assemblies disposed at an equal-angle distance at the razor blade cartridge along a direction in which the razor blade cartridge rotates, at least one pair of razor blades (hereinafter referred to as first razor blades) being arranged in an overlapping manner at a predetermined distance at the razor blade assembly along a radius direction of the razor blade cartridge. The electric rotary razor of the present invention has a structure of a wet shaver where multiple razor blades are arranged, and uses the motor to turn the razor blade cartridge during shaving for user convenience and thorough shaving. The multi-blade razor blade assembly alleviates a dermal stimulation, minimizes a possibility of a scar, and does not require shaving cream, making shaving convenient and unhindered by time and space.

    摘要翻译： 本发明涉及一种多叶片电动旋转剃须刀，其包括由马达旋转的剃刀刀片盒，以及至少一对剃刀刀片组件，其在剃须刀片刀片架上以等距离的距离沿着 剃刀刀片刀片架旋转，至少一对剃刀刀片（以下称为第一剃刀刀片）沿剃刀刀片刀片组件的半径方向以剃刀刀片组件以预定距离重叠布置。 本发明的电动旋转剃刀具有布置多个剃刀刀片的湿式剃须刀的结构，并且在剃刮期间使用电动机来转动剃刀刀片盒以便于用户方便和彻底的剃刮。 多叶片剃刀刀片组件减轻皮肤刺激，使疤痕的可能性最小化，并且不需要剃须膏，使剃须方便和不受时间和空间的妨碍。

    Method and apparatus for transmitting digital broadcasting stream using linking information about multi-view video stream, and method and apparatus for receiving the same
    77.
    发明授权
    Method and apparatus for transmitting digital broadcasting stream using linking information about multi-view video stream, and method and apparatus for receiving the same 有权
    使用关于多视点视频流的链接信息发送数字广播流的方法和装置，以及用于接收数字广播流的方法和装置

    公开(公告)号：US09055280B2

    公开(公告)日：2015-06-09

    申请号：US13016339

    申请日：2011-01-28

    申请人： Yong-tae Kim ,  Jae-jun Lee ,  Yong-seok Jang ,  Kil-soo Jung ,  Hong-seok Park

    发明人： Yong-tae Kim ,  Jae-jun Lee ,  Yong-seok Jang ,  Kil-soo Jung ,  Hong-seok Park

    IPC分类号： H04N13/00 ,  H04N13/04

    CPC分类号： H04N13/161 ,  H04N13/139 ,  H04N13/194 ,  H04N13/356 ,  H04N19/46 ,  H04N19/597 ,  H04N19/70 ,  H04N2213/003

    摘要： A digital broadcasting stream transmitting method and a digital broadcasting stream receiving method and apparatus for providing three-dimensional (3D) video services are provided. The transmitting method including: generating a plurality of elementary streams (ESs) for a plurality of pieces of video information including at least one of information about a base-view video of a 3D video, information about an additional-view video corresponding to the base-view video, and a two-dimensional (2D) video having a different view from views of the 3D video; multiplexing the plurality of ESs with link information for identifying at least one piece of video information linked with the plurality of pieces of video information, to generate at least one transport stream (TS); and transmitting the generated at least one TS via at least one channel.

    摘要翻译： 提供了一种用于提供三维（3D）视频服务的数字广播流发送方法和数字广播流接收方法和装置。 所述发送方法包括：为多条视频信息生成多个基本流（ES），所述多个视频信息包括关于3D视频的基本视点的信息中的至少一个，关于与所述基础相关的附加视频视频的信息 视频视频和具有与3D视频的视图不同的视图的二维（2D）视频; 将多个ES复用到用于识别与多条视频信息链接的至少一条视频信息的链接信息，以产生至少一个传输流（TS）; 以及经由至少一个信道发送所生成的至少一个TS。

    TRANSMITTER FOR TRANSMITTING DATA FOR CONSTITUTING CONTENT, RECEIVER FOR RECEIVING AND PROCESSING DATA, AND METHOD THEREFOR
    79.
    发明申请
    TRANSMITTER FOR TRANSMITTING DATA FOR CONSTITUTING CONTENT, RECEIVER FOR RECEIVING AND PROCESSING DATA, AND METHOD THEREFOR 有权
    用于传输内容数据的发送机，接收和处理数据的接收方及其方法

    公开(公告)号：US20130251342A1

    公开(公告)日：2013-09-26

    申请号：US13992297

    申请日：2011-12-07

    申请人： Hong-Seok Park ,  Yong-Tae Kim ,  Jae-Jun Lee ,  Moon-Seok Jang ,  Yu-Sung Joo

    发明人： Hong-Seok Park ,  Yong-Tae Kim ,  Jae-Jun Lee ,  Moon-Seok Jang ,  Yu-Sung Joo

    IPC分类号： H04N13/00

    CPC分类号： H04N13/189 ,  H04N21/4307 ,  H04N21/4331 ,  H04N21/4627 ,  H04N21/631 ,  H04N21/8355

    摘要： A receiver is disclosed. The receiver comprises: a first receiving unit for receiving non-real-time data for constituting multimedia content; a storage unit for storing the non-real-time data; a second receiving unit for receiving real-time data for constituting multimedia content; a data processing unit which, if the real-time data has been received, detects the non-real-time data, in conjunction with the real-time data, from among the data stored in the storage unit, binds the detected non-real-time data and the received real-time data, and outputs multimedia content; and a control unit for controlling the data processing unit so as to restrict the output of the non-real-time data prior to the time of the output of the real-time data.

    摘要翻译： 公开了接收机。 接收机包括：第一接收单元，用于接收用于构成多媒体内容的非实时数据; 用于存储非实时数据的存储单元; 第二接收单元，用于接收用于构成多媒体内容的实时数据; 数据处理单元，如果已经接收到实时数据，则结合实时数据，从存储在存储单元中的数据中检测非实时数据，将检测到的非真实数据 时间数据和接收到的实时数据，并输出多媒体内容; 以及控制单元，用于控制数据处理单元，以便在实时数据的输出时间之前限制非实时数据的输出。

    THREE-DIMENSIONAL IMAGE DATA ENCODING AND DECODING METHOD AND DEVICE
    80.
    发明申请
    THREE-DIMENSIONAL IMAGE DATA ENCODING AND DECODING METHOD AND DEVICE 审中-公开
    三维图像数据编码和解码方法和设备

    公开(公告)号：US20130028315A1

    公开(公告)日：2013-01-31

    申请号：US13641387

    申请日：2011-04-13

    申请人： Hong-Seok Park ,  Jae-Jun Lee ,  Yong-Tae Kim ,  Dae-jong Lee

    发明人： Hong-Seok Park ,  Jae-Jun Lee ,  Yong-Tae Kim ,  Dae-jong Lee

    IPC分类号： H04N11/04 ,  G06K9/36

    CPC分类号： H04N21/816 ,  H04N19/188 ,  H04N19/44 ,  H04N19/46 ,  H04N19/597 ,  H04N19/70

    摘要： A method and apparatus for encoding and decoding three-dimensional (3D) image data is provided. The method of encoding 3D image data uses a data unit that includes a header area and a data area. Type information which indicates a type of data included in the data area is included in the header area, includes: encoding reference view image data and additional view image data for providing a 3D image; generating a first data unit by adding to the reference view image data a header which includes first unit type information from among pieces of type information defined in a legacy device; and generates a second data unit by adding to the additional view image data a header which includes second unit type information from among pieces of type information not defined in the legacy device.

    摘要翻译： 提供了一种用于对三维（3D）图像数据进行编码和解码的方法和装置。 3D图像数据的编码方法使用包括标题区域和数据区域的数据单元。 包括在头部区域中的包含在数据区域中的数据类型的类型信息包括：编码参考视图图像数据和用于提供3D图像的附加视图图像数据; 通过向所述参考视图图像数据添加包括在传统设备中定义的多个类型信息中的第一单元类型信息的报头来产生第一数据单元; 并且通过向附加视图图像数据添加包括来自未在传统设备中定义的多个类型信息中的第二单元类型信息的报头来生成第二数据单元。