公开(公告)号：US6151272A

公开(公告)日：2000-11-21

申请号：US356269

申请日：1999-07-16

Applicant: One-gyun La ,  Jung-bae Lee ,  Si-yeol Lee

Inventor： One-gyun La ,  Jung-bae Lee ,  Si-yeol Lee

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/12 ,  G11C29/48 ,  G11C8/00

CPC classification number: G11C7/1093 ,  G11C29/48 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/222

Abstract: Integrated circuit memory devices that utilize preferred masking techniques include a memory cell array and a mask signal generator that generates first and second internal data masking signals in response to at least one single data rate mode signal. A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals is active. This ability to mask data facilitates operation of the memory device in a specialized single data rate mode for testing using conventional test equipment.

Abstract translation: 利用优选掩蔽技术的集成电路存储器件包括存储单元阵列和屏蔽信号发生器，其响应于至少一个单个数据速率模式信号产生第一和第二内部数据屏蔽信号。 还提供数据控制器，用于当第一和第二内部数据屏蔽信号不活动时将输入写入数据传送到存储单元阵列，并且当第一和第二数据屏蔽信号中的一个第一和第二 内部数据屏蔽信号有效。 掩蔽数据的这种能力有助于以专门的单数据速率模式进行存储器件的操作，以便使用常规测试设备进行测试。

公开(公告)号：US6018259A

公开(公告)日：2000-01-25

申请号：US998326

申请日：1997-12-24

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C11/407 ,  G06F1/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/417 ,  H03K5/13 ,  H03L7/00 ,  H03L7/06 ,  H03L7/081 ,  H03L7/087 ,  H04L7/02 ,  H03K5/14

CPC classification number: G11C7/222 ,  G11C7/22 ,  H03K5/133 ,  H03L7/0814 ,  H03L7/087

Abstract: A phase locked delay circuit which reduces the layout area of a semiconductor device includes a delay buffer, a main delay portion, a delay line, means for detecting phase synchronization, a switching unit, a clock driver, and a flag signal generator. The delay buffer receives an external system clock signal, delays the received signal for a predetermined first delay time, and buffers the delayed signal. The main delay portion delays the output of the delay buffer for a predetermined second delay time in response to a flag signal, or bypasses the output of the delay buffer. The delay line sequentially delays the output of the main delay portion for a unit time. The phase synchronization detecting means detects a third delay time required for synchronizing the output of the main delay portion with the output of the delay buffer in response to the flag signal, using the output of the delay line, and activates a corresponding enable signal. The flag signal generator activates the flag signal only when the phase synchronization detecting means detects the third delay time. The switching unit is controlled by enable signals and switches a corresponding signal among signals output by the delay line. The clock driver delays the output of the switching for a fourth delay time and outputs the delayed signal as an internal clock signal.

Abstract translation: 降低半导体器件的布局面积的锁相延迟电路包括延迟缓冲器，主延迟部分，延迟线，用于检测相位同步的装置，切换单元，时钟驱动器和标志信号发生器。 延迟缓冲器接收外部系统时钟信号，将接收到的信号延迟预定的第一延迟时间，并缓冲延迟的信号。 响应于标志信号，主延迟部分延迟延迟缓冲器的输出达预定的第二延迟时间，或者绕过延迟缓冲器的输出。 延迟线依次将主延迟部分的输出延迟一个单位时间。 相位同步检测装置使用延迟线的输出，根据标志信号检测使主延迟部分的输出与延迟缓冲器的输出同步的第三延迟时间，并且激活相应的使能信号。 只有当相位同步检测装置检测到第3延迟时间时，标志信号发生器激活标志信号。 开关单元由使能信号控制，并在延迟线输出的信号之间切换相应的信号。 时钟驱动器延迟第四个延迟时间的开关输出，并将延迟的信号作为内部时钟信号输出。

公开(公告)号：US20150339255A1

公开(公告)日：2015-11-26

申请号：US14818586

申请日：2015-08-05

Applicant: Young Chul CHO ,  Jung Bae LEE ,  Jung Hwan CHOI

Inventor： Young Chul CHO ,  Jung Bae LEE ,  Jung Hwan CHOI

IPC: G06F13/42 ,  G05F1/625

CPC classification number: G06F13/16 ,  G05F1/625 ,  G06F1/3287 ,  G06F13/4068 ,  G06F13/4221 ,  H03K19/0005 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Abstract translation: 操作输入/输出接口的方法包括根据模式选择信号选择多个输出驱动器电路中的一个，并且使用多个输出驱动器电路中选择的一个输出驱动器电路来输出数据信号。 另一种操作方法包括根据所接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的片上终端（ODT）电路。 另一种操作方法包括基于接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的ODT电路。

公开(公告)号：US09036439B2

公开(公告)日：2015-05-19

申请号：US13548484

申请日：2012-07-13

Applicant: Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

Inventor： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

IPC: G11C29/08 ,  G11C7/00 ,  G11C29/50 ,  G11C11/406 ,  G11C5/04 ,  G11C11/40

CPC classification number: G11C29/50016 ,  G11C5/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

Abstract: A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Abstract translation: 具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作 根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

公开(公告)号：US20140152340A1

公开(公告)日：2014-06-05

申请号：US14093916

申请日：2013-12-02

Applicant: Young Chul CHO ,  Jung Bae LEE ,  Jung Hwan CHOI

Inventor： Young Chul CHO ,  Jung Bae LEE ,  Jung Hwan CHOI

IPC: H03K19/00

CPC classification number: G06F13/16 ,  G05F1/625 ,  G06F1/3287 ,  G06F13/4068 ,  G06F13/4221 ,  H03K19/0005 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Abstract translation: 操作输入/输出接口的方法包括根据模式选择信号选择多个输出驱动器电路中的一个，并且使用多个输出驱动器电路中选择的一个输出驱动器电路来输出数据信号。 另一种操作方法包括根据所接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的片上终端（ODT）电路。 另一种操作方法包括基于接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的ODT电路。

公开(公告)号：US08654864B2

公开(公告)日：2014-02-18

申请号：US13775543

申请日：2013-02-25

Applicant: Hoe-Ju Chung ,  Jung-Bae Lee

Inventor： Hoe-Ju Chung ,  Jung-Bae Lee

IPC: H04B14/06

CPC classification number: H04L25/0264 ,  H04L25/0272

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract translation: 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US08520461B2

公开(公告)日：2013-08-27

申请号：US12832208

申请日：2010-07-08

Applicant: Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

Inventor： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C17/16 ,  G11C2211/4061

Abstract: A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together.

Abstract translation: 存储器设备识别包含不合标准存储器单元的存储器块。 然后，存储器件在刷新操作期间确定应用于存储器块的行地址代码。 行地址代码确定存储器块的哪些存储器块被一起刷新。 行地址码被设计为确保具有不同于其它单元的频率更新的不合格存储器单元的存储器块被一起刷新，而没有不合格存储器单元的存储器块被刷新在一起。

公开(公告)号：US20130163692A1

公开(公告)日：2013-06-27

申请号：US13775543

申请日：2013-02-25

Applicant: Hoe-ju CHUNG ,  Jung-bae LEE

Inventor： Hoe-ju CHUNG ,  Jung-bae LEE

IPC: H04B1/02

CPC classification number: H04L25/0264 ,  H04L25/0272

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract translation: 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US08335115B2

公开(公告)日：2012-12-18

申请号：US12781936

申请日：2010-05-18

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C7/10

CPC classification number: G11C7/1078 ,  G11C5/04 ,  G11C7/1084

Abstract: A semiconductor memory module includes a memory module board having at least one semiconductor memory device, an advanced memory buffer (AMB) for receiving the data and the command/address signal from a host and providing the data and the command/address signal to the at least one semiconductor memory device, and a second termination resistor unit located on the memory module board and electrically connected to the AMB. The at least one semiconductor memory device includes a data input buffer for receiving data via a first input terminal and receiving a first reference voltage via a second input terminal, a command/address input buffer for receiving a command/address signal via a first input terminal and receiving a second reference voltage via a second input terminal, and a first termination resistor unit connected to the first input terminal of the data input buffer.

Abstract translation: 半导体存储器模块包括具有至少一个半导体存储器件的存储器模块板，用于从主机接收数据和命令/地址信号的高级存储器缓冲器（AMB），并将数据和命令/地址信号提供给at 至少一个半导体存储器件，以及位于存储器模块板上并电连接到AMB的第二终端电阻器单元。 所述至少一个半导体存储器件包括用于经由第一输入端子接收数据并经由第二输入端子接收第一参考电压的数据输入缓冲器，用于经由第一输入端子接收命令/地址信号的命令/地址输入缓冲器 以及经由第二输入端子接收第二参考电压，以及连接到数据输入缓冲器的第一输入端的第一终端电阻器单元。

公开(公告)号：US08208335B2

公开(公告)日：2012-06-26

申请号：US12821515

申请日：2010-06-23

Applicant: Dong-Hyuk Lee ,  Jung-Bae Lee ,  Doo-Gon Kim ,  Cheol Kim

Inventor： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Doo-Gon Kim ,  Cheol Kim

IPC: G11C7/00

CPC classification number: G11C29/50 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/24 ,  G11C29/50016 ,  G11C2211/4061

Abstract: A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block.

Abstract translation: 半导体存储器件包括具有多个块的单元阵列单元，每个单元具有多个块，以及刷新控制器，被配置为将至少一个块设置为测试块，对除了测试之外的块执行刷新操作 在自刷新操作期间块，确定测试块的刷新周期，然后将另一个块设置为测试块。