公开(公告)号：US06313670B1

公开(公告)日：2001-11-06

申请号：US09433099

申请日：1999-11-03

申请人： Ki-whan Song ,  Chan-jong Park

发明人： Ki-whan Song ,  Chan-jong Park

IPC分类号： H03K300

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069

摘要： A current control circuit capable of minimizing changes in an output high voltage VOH and an output low voltage VOL and quickly and accurately bringing a divided voltage to a steady state, and a packet-type semiconductor memory device including the current control circuit. The current control circuit includes a first differential amplification type buffer for transmitting the voltage of a first pad, that is, the output high voltage VOH, without change in response to a current control enable signal, a second differential amplification type buffer for transmitting the voltage of a second pad, that is, the output low voltage VOL, without change in response to the current control enable signal, and a voltage divider for dividing a voltage ranging between the voltage outputs of the first and second differential amplification buffers, and outputting the divided voltage. Accordingly, in the packet-type semiconductor memory device including the current control circuit, the current control circuit minimizes changes in the output high voltage VOH and the output low voltage VOL and quickly and accurately brings a divided voltage to a steady state, so that the current driving capability of an output driver for driving the second pad can be quickly controlled.

摘要翻译： 一种电流控制电路，其能够使输出高电压VOH和输出低电压VOL的变化最小化，并将分压后的电压快速准确地设定为稳定状态，以及包括电流控制电路的分组型半导体存储器件。 电流控制电路包括：第一差分放大型缓冲器，用于传输第一焊盘的电压，即输出高电压VOH，而不改变响应于电流控制使能信号;第二差分放大型缓冲器，用于传输电压 的第二焊盘，即输出低电压VOL，而不响应于电流控制使能信号而变化;以及分压器，用于分压第一和第二差分放大缓冲器的电压输出之间的电压范围，并输出 分压。 因此，在包括电流控制电路的分组型半导体存储器件中，电流控制电路使输出高电压VOH和输出低电压VOL的变化最小化，并且将分压后的电压快速准确地导入稳定状态， 可以快速地控制用于驱动第二焊盘的输出驱动器的电流驱动能力。

公开(公告)号：US09042167B2

公开(公告)日：2015-05-26

申请号：US13540979

申请日：2012-07-03

申请人： Duk-Min Kwon ,  Ki Whan Song

发明人： Duk-Min Kwon ,  Ki Whan Song

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C13/00

CPC分类号： G11C5/145 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097

摘要： A phase change memory device including a voltage generator that generates an operating voltage by generating at least one modified clock signal, a pulse width of which is maintained constant for at least one clock cycle in response to a pump enable signal being enabled, from at least one reference clock signal, and performing a pump operation on a power supply voltage according to the at least one modified clock signal; and a memory cell array that includes a plurality of phase change memory cells connected between word lines and bit lines. The operating voltage is applied to the memory cell array so as to perform a data access operation.

摘要翻译： 一种相变存储器件，包括电压发生器，该电压发生器通过产生至少一个经修改的时钟信号产生工作电压，所述修改的时钟信号至少在一个时钟周期内保持恒定至少一个时钟周期， 一个参考时钟信号，并且根据至少一个修改的时钟信号对电源电压执行泵操作; 以及包括连接在字线和位线之间的多个相变存储单元的存储单元阵列。 将工作电压施加到存储单元阵列，以执行数据存取操作。

公开(公告)号：US08837234B2

公开(公告)日：2014-09-16

申请号：US13209010

申请日：2011-08-12

申请人： Yu Hwan Ro ,  Beak Hyung Cho ,  Ki Whan Song ,  Young Don Choi

发明人： Yu Hwan Ro ,  Beak Hyung Cho ,  Ki Whan Song ,  Young Don Choi

IPC分类号： G11C7/00 ,  G11C11/4094 ,  G11C7/02 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4097

CPC分类号： G11C11/4094 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4097

摘要： A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.

摘要翻译： 提供了一种存储器件，其包括多个全局位线，放电线，配置成响应于放电使能信号将多个全局位线连接到放电线的开关电路，配置为施加的第一放电电路 第一电压，其高于对所述放电线的接地电压;预充电电路，被配置为对所述多个全局位线中的所选择的全局位线施加预充电电压;以及第二放电电路，被配置为将所选择的全局位 线路到高于接地电压的第二电压。

公开(公告)号：US08772872B2

公开(公告)日：2014-07-08

申请号：US12588276

申请日：2009-10-09

申请人： Nam-Kyun Tak ,  Ki-Whan Song

发明人： Nam-Kyun Tak ,  Ki-Whan Song

IPC分类号： H01L27/12

CPC分类号： H01L29/7841 ,  H01L21/28114 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/66553 ,  H01L29/7843 ,  H01L29/7846

摘要： Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions.

摘要翻译： 提供了具有晶体管的晶体管，具有晶体管的半导体存储单元及其形成方法，晶体管可以包括具有第一半导体区域的半导体衬底。 栅极图案可以设置在第一半导体区域上。 间隔图案可以各自设置在栅极图案的侧壁上。 第二半导体区域和第三半导体区域可以设置在半导体衬底中。 第二半导体区域可以设置在间隔图案下方。 第三半导体区域可以被布置成与第二半导体区域相邻。 第一半导体区域可以具有比第二半导体区域更高的杂质离子浓度。

公开(公告)号：US08575672B2

公开(公告)日：2013-11-05

申请号：US13047403

申请日：2011-03-14

申请人： Ki-whan Song ,  Byung-Gook Park

发明人： Ki-whan Song ,  Byung-Gook Park

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.

公开(公告)号：US08503218B2

公开(公告)日：2013-08-06

申请号：US13155492

申请日：2011-06-08

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C11/06 ,  G11C7/10

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038

摘要： A nonvolatile memory device includes: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the write global bit line and disposed on a first side of the memory array; and a read circuit connected to the read global bit line and disposed on a second side of the memory array opposite the first side of the memory array, wherein each of the memory banks extends in a second direction different from the first direction and comprises a plurality of nonvolatile memory cells, each of the nonvolatile memory cells having a variable resistive element whose resistance value varies according to data stored therein.

摘要翻译： 非易失性存储器件包括：存储器阵列，包括沿第一方向布置的多个存储体; 写入全局位线和在第一方向上延伸以由存储体共享的读取全局位线; 写入电路，连接到写入全局位线并且设置在存储器阵列的第一侧上; 以及读取电路，连接到读取的全局位线并且设置在与存储器阵列的第一侧相对的存储器阵列的第二侧上，其中每个存储体沿与第一方向不同的第二方向延伸并且包括多个 的非易失性存储单元，每个非易失性存储单元具有可变电阻元件，其电阻值根据存储在其中的数据而变化。

公开(公告)号：US08134202B2

公开(公告)日：2012-03-13

申请号：US12453036

申请日：2009-04-28

申请人： Nam-Kyun Tak ,  Ki-Whan Song

发明人： Nam-Kyun Tak ,  Ki-Whan Song

IPC分类号： H01L29/792

CPC分类号： H01L29/7841 ,  H01L29/785

摘要： A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern.

摘要翻译： 提供其数据存储能力增加并且漏电流减小的无电容器一晶体管（1T）半导体器件。 电容器1T半导体器件包括形成在基板上的掩埋绝缘层，形成在掩埋绝缘层上的有源区，并且包括源区域，漏极区域和形成在源极区域与漏极区域之间的浮体，以及 形成在所述浮体上的栅极图案，其中，所述浮体包括具有与所述源极区域和所述漏极区域中的一个相同的顶部高度的主浮体，以及形成在所述主浮体和所述栅极之间的第一上浮体 模式。

公开(公告)号：US08120979B2

公开(公告)日：2012-02-21

申请号：US12591254

申请日：2009-11-13

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4097 ,  G11C2207/002

摘要： The semiconductor memory device includes a memory cell array and a switching circuit. The memory cell array includes a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines. The switching circuit is configured to respectively connect the first local bit lines to first global bit lines during a first sensing period, and to respectively connect the second local bit lines to second global bit lines during a second sensing period of a reading operation. The semiconductor memory device further includes a sensing circuit configured to sense and amplify data from the first global bit lines during the first sensing period, and to sense and amplify data from the second global bit lines during the second sensing period of the reading operation.

摘要翻译： 半导体存储器件包括存储单元阵列和开关电路。 存储单元阵列包括连接在字线和第一局部位线之间的多个第一存储单元，以及连接在字线和第二局部位线之间的多个第二存储单元。 开关电路被配置为在第一感测周期期间将第一本地位线分别连接到第一全局位线，并且在读取操作的第二感测周期期间将第二局部位线分别连接到第二全局位线。 半导体存储器件还包括感测电路，其被配置为在第一感测周期期间感测和放大来自第一全局位线的数据，并且在读取操作的第二感测周期期间感测和放大来自第二全局位线的数据。

公开(公告)号：US20120039141A1

公开(公告)日：2012-02-16

申请号：US13209010

申请日：2011-08-12

申请人： Yu Hwan RO ,  Beak Hyung CHO ,  Ki Whan SONG ,  Young Don CHOI

发明人： Yu Hwan RO ,  Beak Hyung CHO ,  Ki Whan SONG ,  Young Don CHOI

IPC分类号： G11C7/12

CPC分类号： G11C11/4094 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4097

摘要： A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.

摘要翻译： 提供了一种存储器件，其包括多个全局位线，放电线，配置成响应于放电使能信号将多个全局位线连接到放电线的开关电路，配置为施加的第一放电电路 第一电压，其高于对所述放电线的接地电压;预充电电路，被配置为对所述多个全局位线中的所选择的全局位线施加预充电电压;以及第二放电电路，被配置为将所选择的全局位 线路到高于接地电压的第二电压。

公开(公告)号：US07777999B2

公开(公告)日：2010-08-17

申请号：US11969966

申请日：2008-01-07

申请人： Myoung-Gon Kang ,  Ki-Whan Song

发明人： Myoung-Gon Kang ,  Ki-Whan Song

IPC分类号： H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： An electrostatic discharge (ESD) protection device includes an I/O terminal structure and a current discharge structure. The current discharge structure includes a conductive region separated from a bridge region by a gate electrode, a well region formed below the conductive region, another well region separated from the well region by another conductive region, and multiple additional conductive regions implementing dual current discharge paths through another well region.

摘要翻译： 静电放电（ESD）保护装置包括I / O端子结构和电流放电结构。 电流放电结构包括通过栅极电极与桥接区域分离的导电区域，形成在导电区域下方的阱区域，通过另一导电区域与阱区域分离的另一阱区域以及实现双电流放电路径的多个附加导电区域 通过另一个井区。