公开(公告)号：US20250124987A1

公开(公告)日：2025-04-17

申请号：US18990013

申请日：2024-12-20

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Thomas Fiala ,  Jian Huang ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/16

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations, including: determining a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.

公开(公告)号：US20250124963A1

公开(公告)日：2025-04-17

申请号：US18744988

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Yang Lu

IPC: G11C11/406

Abstract: Apparatuses and methods for per-row count based refresh target identification with sorting. A memory includes a number of word lines each associated with a row address and a count value. A targeted refresh queue stores the highest count values and their row addresses as an ordered list. For example the list may be sorted from highest count value to lowest count value. During a targeted refresh operation, the row address at a top of the queue is used for refresh operations and removed from the queue. When a row and count value are added to the queue, the queue is re-sorted.

公开(公告)号：US20250123770A1

公开(公告)日：2025-04-17

申请号：US19003039

申请日：2024-12-27

Applicant: Micron Technology, Inc.

Inventor： Laurent Isenegger

IPC: G06F3/06

Abstract: A request can be provided, from a front-end of a memory sub-system, to a processing device of the memory sub-system and deleting the request from a buffer of the front-end of the memory sub-system. Responsive to deleting the request from the buffer, determining a first quantity of requests in the buffer and responsive to deleting the requests from the buffer, determining a second quantity of outstanding requests in the back-end of the memory sub-system. Responsive to deleting the request from the buffer and providing the request to the processing device, determining whether to provide a response to a host, wherein the response includes an indication of the quantity of requests in the buffer and of outstanding requests in a back-end of the memory sub-system, based on a comparison of the second quantity of outstanding requests to a threshold.

公开(公告)号：US20250123765A1

公开(公告)日：2025-04-17

申请号：US18830260

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Bo Zhou ,  Caixia Yang

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.

公开(公告)号：US12279410B2

公开(公告)日：2025-04-15

申请号：US17705680

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Gurtej S. Sandhu ,  Scott E. Sills ,  Si-Woo Lee ,  John A. Smythe, III

IPC: H10B12/00 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

公开(公告)号：US12277972B2

公开(公告)日：2025-04-15

申请号：US17512597

申请日：2021-10-27

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: Methods, systems, and devices for source line configurations for a memory device are described. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled with the floating gate of the first transistor. The memory cell may be coupled with a word line, a digit line, and a source line. During a write operation, the source line may be clamped to the digit line using one or more memory cells in the memory device. During a read operation, the source line may be grounded using one or more memory cells in the memory device.

公开(公告)号：US20250118722A1

公开(公告)日：2025-04-10

申请号：US18982102

申请日：2024-12-16

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/00

Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

公开(公告)号：US20250118693A1

公开(公告)日：2025-04-10

申请号：US18776197

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Kunal R. Parekh ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: Methods, systems, and devices for techniques for semiconductor die coupling in stacked memory architectures are described. A semiconductor system may include a semiconductor unit formed by multiple semiconductor dies, where each semiconductor die may be fabricated to be individually separable. Each semiconductor die may include a respective portion of circuitry associated with the semiconductor unit. The multiple semiconductor dies may be coupled with a carrier, and each semiconductor die may be coupled (e.g., electrically, communicatively) with at least one other semiconductor die. At least some of the semiconductor dies may be coupled with a respective set of one or more memory arrays, where each memory array may be operable based on the coupling between the multiple semiconductor dies.

公开(公告)号：US20250118653A1

公开(公告)日：2025-04-10

申请号：US18981288

申请日：2024-12-13

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending extend farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：US20250118385A1

公开(公告)日：2025-04-10

申请号：US18923244

申请日：2024-10-22

Applicant: Micron Technology, Inc.

Inventor： Chunqiang Weng ,  Jingwei Cheng

IPC: G11C29/56

Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.