公开(公告)号：US20080160759A1

公开(公告)日：2008-07-03

申请号：US11824218

申请日：2007-06-29

Applicant: Min-Suk Lee ,  Jae-Young Lee

Inventor： Min-Suk Lee ,  Jae-Young Lee

IPC: H01L21/44

CPC classification number: H01L21/76897 ,  H01L21/31144

Abstract: A method for fabricating a semiconductor device includes forming an etch barrier layer over a semi-finished substrate that includes a plurality of patterns, forming an insulation layer over the etch barrier layer, planarizing the insulation layer, recessing a portion of the planarized insulation layer, forming a hard mask pattern over the recessed and planarized insulation layer, etching the recessed insulation layer to form a contact hole, etching the etch barrier layer formed over a bottom portion of the contact hole, and forming a plug contact in the contact hole.

Abstract translation: 一种用于制造半导体器件的方法包括在半成品衬底上形成蚀刻阻挡层，所述半成品衬底包括多个图案，在所述蚀刻阻挡层上形成绝缘层，平坦化所述绝缘层，使所述平坦化绝缘层的一部分凹陷， 在凹陷和平坦化的绝缘层上形成硬掩模图案，蚀刻凹陷绝缘层以形成接触孔，蚀刻形成在接触孔的底部上的蚀刻阻挡层，以及在接触孔中形成插头接触。

公开(公告)号：US20070063653A1

公开(公告)日：2007-03-22

申请号：US11516059

申请日：2006-09-06

Applicant: Sang-Hoon Yim ,  Yoon-Chang Kim ,  Min-Suk Lee ,  Hyoung-Bin Park

Inventor： Sang-Hoon Yim ,  Yoon-Chang Kim ,  Min-Suk Lee ,  Hyoung-Bin Park

IPC: H01J17/49

CPC classification number: H01J11/22 ,  H01J11/12 ,  H01J11/16 ,  H01J61/0672 ,  H01J61/305 ,  H01J61/70 ,  H01J2211/245 ,  H01J2211/265

Abstract: A Plasma Display Panel (PDP) includes a dielectric layer having a plurality of dielectric-layer perforated holes arranged in a matrix; and upper and lower electrode layers having electrode-layer perforated holes connected to the dielectric-layer perforated holes and arranged on both surfaces of the dielectric layer; the upper electrode layer includes a plurality of first electrodes extending in a first direction, the plurality of first electrodes surrounding a group of electrode-layer perforated holes arranged in the first direction; and the lower electrode layer includes a plurality of second electrodes extending in a second direction different from the first direction, the plurality of second electrodes surrounding a group of electrode-layer perforated holes arranged in the second direction. Individual electrodes surrounding the electrode-layer perforated holes protrude from the dielectric layer toward the centers of the perforated holes such that a facing discharge is generated between the upper and lower individual electrodes, resulting in a PDP having stable characteristics and high efficiency and having a simple structure.

Abstract translation: 等离子体显示面板（PDP）包括具有布置在矩阵中的多个电介质层穿孔的电介质层; 上电极层和下电极层具有连接到电介质层穿孔的电极层穿孔，并布置在电介质层的两个表面上; 所述上电极层包括沿第一方向延伸的多个第一电极，所述多个第一电极围绕沿所述第一方向布置的一组电极层穿孔; 并且所述下电极层包括在与所述第一方向不同的第二方向上延伸的多个第二电极，所述多个第二电极围绕沿所述第二方向布置的一组电极层穿孔。 电极层穿孔的周围的单个电极从电介质层朝向穿孔的中心突出，从而在上下单个电极之间产生面对放电，导致具有稳定特性和高效率的PDP，并且具有简单的 结构体。

公开(公告)号：US07179744B2

公开(公告)日：2007-02-20

申请号：US10617182

申请日：2003-07-11

Applicant: Sung-Kwon Lee ,  Min-Suk Lee ,  Sang-Ik Kim

Inventor： Sung-Kwon Lee ,  Min-Suk Lee ,  Sang-Ik Kim

IPC: H01L21/302 ,  C09K13/00

CPC classification number: H01L27/105 ,  H01L21/31111 ,  H01L27/1052

Abstract: A method for fabricating a semiconductor device includes the steps of: (a) forming a plurality of conductive patterns on a substrate in a cell region and a peripheral circuit region; (b) forming an insulation layer on an entire surface of the resulting structure from the step. (a); (c) forming a plurality of plugs in the cell region and simultaneously forming a dummy pattern in a region between the cell region and the peripheral circuit region, each plug and the dummy pattern being contacted to the substrate allocated between the conductive patterns by passing through the insulation layer; (d) forming a photoresist pattern masking the resulting structure in the cell region; and (e) removing the insulation layer in the peripheral circuit region by performing a wet etching process with use of the photoresist pattern as an etch mask to thereby expose a surface of the substrate in the peripheral circuit region.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：（a）在单元区域和外围电路区域中的衬底上形成多个导电图案; （b）从所述台阶在所得结构的整个表面上形成绝缘层。 （一个）; （c）在单元区域中形成多个插塞，并且在单元区域和外围电路区域之间的区域中同时形成虚设图案，每个插头和虚设图案通过穿过与导电图案之间分配的基板接触 绝缘层; （d）形成掩蔽所述细胞区域中的所得结构的光致抗蚀剂图案; 和（e）通过使用光致抗蚀剂图案作为蚀刻掩模进行湿式蚀刻处理，从而在外围电路区域中露出基板的表面，从而去除外围电路区域中的绝缘层。

公开(公告)号：US20060189080A1

公开(公告)日：2006-08-24

申请号：US11363811

申请日：2006-02-27

Applicant: Min-Suk Lee ,  Sung-Kwon Lee

Inventor： Min-Suk Lee ,  Sung-Kwon Lee

IPC: H01L21/336

CPC classification number: H01L21/823425 ,  H01L21/31116 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823475

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming at least two gate patterns over a substrate; forming a first sidewall layer over on entire of the substrate structure including gat patterns; forming an insulation layer over the first sidewall layer; selectively removing the insulation layer between the gate patterns to form a contact hole partially exposing the first sidewall layer; forming a second sidewall layer over the first sidewall layer exposed by the contact hole; and removing the first and the second sidewall layers disposed at a bottom portion of the contact hole to expose a selected portion of the substrate between the gate patterns.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括：在衬底上形成至少两个栅极图案; 在包括沟槽图案的整个基板结构上形成第一侧壁层; 在所述第一侧壁层上形成绝缘层; 选择性地去除栅极图案之间的绝缘层，以形成部分暴露第一侧壁层的接触孔; 在由所述接触孔暴露的所述第一侧壁层上形成第二侧壁层; 以及去除设置在接触孔的底部的第一和第二侧壁层，以在栅极图案之间露出衬底的选定部分。

公开(公告)号：US07037850B2

公开(公告)日：2006-05-02

申请号：US10728775

申请日：2003-12-08

Applicant: Sung-Kwon Lee ,  Sang-Ik Kim ,  Min-Suk Lee

Inventor： Sung-Kwon Lee ,  Sang-Ik Kim ,  Min-Suk Lee

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/32139 ,  H01L21/3081

Abstract: The present invention relates to a method for fabricating a semiconductor device with realizable advanced fine patterns. The method includes the steps of: forming a hard mask insulation layer on an etch target layer; forming a hard mask sacrificial layer on the hard mask insulation layer; coating a photoresist on the hard mask insulation layer; performing selectively a photo-exposure process and a developing process to form a photoresist pattern having a first width for forming a line pattern; etching selectively the hard mask sacrificial layer by using the photoresist pattern as an etch mask to form a sacrificial hard mask having a second width; removing the photoresist pattern; etching the hard mask insulation layer by controlling excessive etching conditions with use of the sacrificial hard mask as an etch mask to form a hard mask having a third width; and etching the etch target layer by using the sacrificial hard mask and the hard mask as an etch mask to form the line pattern having a fourth width, wherein the first width is wider than the fourth width.

Abstract translation: 本发明涉及一种制造具有可实现的高精细图案的半导体器件的方法。 该方法包括以下步骤：在蚀刻目标层上形成硬掩模绝缘层; 在硬掩模绝缘层上形成硬掩模牺牲层; 在硬掩模绝缘层上涂覆光致抗蚀剂; 选择性地执行光曝光处理和显影处理，以形成具有用于形成线图案的第一宽度的光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模来选择性地蚀刻硬掩模牺牲层以形成具有第二宽度的牺牲硬掩模; 去除光致抗蚀剂图案; 通过使用牺牲硬掩模作为蚀刻掩模通过控制过多的蚀刻条件来蚀刻硬掩模绝缘层，以形成具有第三宽度的硬掩模; 以及通过使用所述牺牲硬掩模和所述硬掩模作为蚀刻掩模来蚀刻所述蚀刻目标层，以形成具有第四宽度的所述线图案，其中所述第一宽度宽于所述第四宽度。

公开(公告)号：US06972262B2

公开(公告)日：2005-12-06

申请号：US10866488

申请日：2004-06-12

Applicant: Sung-Kwon Lee ,  Min-Suk Lee

Inventor： Sung-Kwon Lee ,  Min-Suk Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/316 ,  H01L21/60 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/823475 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/316 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76897 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved tolerance to a wet cleaning process. For a contact formation such as a gate structure, a bit line or a metal wire, a spin on glass (SOG) layer employed as an inter-layer insulation layer becomes tolerant to the wet cleaning process by allowing even a bottom part of the SOG layer to be densified during a curing process. The SOG layer is subjected to the curing process after a maximum densification thickness of the SOG layer is obtained through a partial removal of the initially formed SOG layer or through a multiple SOG layer each with the maximum densification thickness. After the SOG layer is cured, a self-aligned contact etching process is performed by using a photoresist pattern singly or together with a hard mask.

Abstract translation: 公开了一种制造对湿式清洗工艺具有改善的耐受性的半导体器件的方法。 对于诸如栅极结构，位线或金属线的接触形成，用作层间绝缘层的旋转玻璃（SOG）层通过允许甚至底部的SOG而允许湿式清洗工艺 层在固化过程中被致密化。 在通过部分去除最初形成的SOG层或通过具有最大致密化厚度的多个SOG层获得SOG层的最大致密化厚度之后，对SOG层进行固化过程。 在SOG层固化之后，通过单独使用光致抗蚀剂图案或与硬掩模一起进行自对准接触蚀刻工艺。

公开(公告)号：US20050112869A1

公开(公告)日：2005-05-26

申请号：US10876783

申请日：2004-06-28

Applicant: Sung-Kwon Lee ,  Min-Suk Lee

Inventor： Sung-Kwon Lee ,  Min-Suk Lee

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/31 ,  H01L21/469 ,  H01L21/4763

CPC classification number: H01L21/02063 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31116 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823475

Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.

Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件能够防止层间绝缘层在湿式清洁过程中由于依赖于经历固化过程的SOG层的厚度和克服缺陷而产生的密度差而被损坏 这是由于某个区域的接触开口不正确以及由APL层的微小空隙发生的冲击造成的。 特别地，该方法包括以下步骤：在衬底上形成多个导电结构; 形成旋涂玻璃层; 固化旋涂玻璃层; 在旋涂玻璃层上形成先进的平面化层; 以及通过选择性地蚀刻高级平坦化层和旋涂玻璃层而形成多个接触孔，从而暴露基板的部分。

公开(公告)号：US20050112865A1

公开(公告)日：2005-05-26

申请号：US10880346

申请日：2004-06-30

Applicant: Sung-Kwon Lee ,  Min-Suk Lee

Inventor： Sung-Kwon Lee ,  Min-Suk Lee

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/06

CPC classification number: H01L21/76897 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76834 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10888

Abstract: Disclosed is a method for fabricating a semiconductor device with protected conductive structures. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask insulation layer formed on the conductive layer; forming a first insulation layer on the conductive structures; forming a plurality of plugs contacted to the substrate disposed between the conductive structures by passing through the first insulation layer and having a predetermined height corresponding to a height between the conductive layer and a top of the hard mask insulation layer; forming an attack barrier layer covering top and sidewalls of the hard mask insulation layer; forming a second insulation layer on the attack barrier layer; and selectively etching the second insulation layer to form a contact hole exposing at least one of the plugs.

Abstract translation: 公开了一种制造具有保护导电结构的半导体器件的方法。 该方法包括以下步骤：在衬底上形成多个导电结构，每个导电结构包括形成在导电层上的导电层和硬掩模绝缘层; 在导电结构上形成第一绝缘层; 通过穿过所述第一绝缘层形成与设置在所述导电结构之间的所述衬底接触的多个插塞，并且具有与所述导电层和所述硬掩模绝缘层的顶部之间的高度相对应的预定高度; 形成覆盖所述硬掩模绝缘层的顶部和侧壁的攻击阻挡层; 在所述攻击阻挡层上形成第二绝缘层; 并且选择性地蚀刻第二绝缘层以形成露出至少一个插塞的接触孔。

公开(公告)号：US20050090117A1

公开(公告)日：2005-04-28

申请号：US10748613

申请日：2003-12-29

Applicant: Min-Suk Lee ,  Sung-Kwon Lee

Inventor： Min-Suk Lee ,  Sung-Kwon Lee

IPC: H01L21/8242 ,  H01L21/027 ,  H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76897 ,  H01L21/0276 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

Abstract: The present invention relates to a method for fabricating a semiconductor device with a fine pattern. The method includes the steps of: (a) forming a semiconductor substrate structure including a substrate, a nitride layer for forming a hard mask, a plurality of conductive patterns, an etch stop layer, an inter-layer insulation layer, an anti-reflective coating (ARC) layer and a photoresist pattern; (b) selectively etching the ARC layer and the nitride layer with use of the photoresist pattern as an etch mask to form a hard mask; (c) removing the photoresist pattern and the ARC layer; (d) etching the inter-layer insulation layer disposed between the conductive patterns by using the hard mask as an etch mask to form a contact hole exposing the etch stop layer; (e) removing the etch stop layer formed at a bottom area of the contact hole to expose the substrate; and (f) forming a plug electrically contacted to the exposed substrate, wherein the steps (b) and (d) to (e) proceeds in an in situ condition.

Abstract translation: 本发明涉及一种具有精细图案的半导体器件的制造方法。 该方法包括以下步骤：（a）形成半导体衬底结构，其包括衬底，用于形成硬掩模的氮化物层，多个导电图案，蚀刻停止层，层间绝缘层，抗反射层 涂层（ARC）层和光致抗蚀剂图案; （b）使用光致抗蚀剂图案作为蚀刻掩模来选择性地蚀刻ARC层和氮化物层以形成硬掩模; （c）去除光致抗蚀剂图案和ARC层; （d）通过使用硬掩模作为蚀刻掩模蚀刻设置在导电图案之间的层间绝缘层，以形成暴露蚀刻停止层的接触孔; （e）去除形成在接触孔的底部区域处的蚀刻停止层，以露出衬底; 和（f）形成与暴露的基底电接触的插塞，其中步骤（b）和（d）至（e）以原位状态进行。

公开(公告)号：US20050090055A1

公开(公告)日：2005-04-28

申请号：US10925856

申请日：2004-08-24

Applicant: Min-Suk Lee ,  Tae-Woo Jung ,  Sung-Kwon Lee

Inventor： Min-Suk Lee ,  Tae-Woo Jung ,  Sung-Kwon Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  Y10S438/952

Abstract: A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

Abstract translation: 一种制造半导体器件的方法，该半导体器件能够防止硬掩模被提起并且图案有缺陷。 特别地，首先将形成在设置有导电结构的基板结构上的层间绝缘层和蚀刻停止层平坦化。 然后，通过使用光致抗蚀剂图案和抗反射涂层作为蚀刻掩模来形成由氮化物基材料制成的硬掩模。 在硬掩模形成之后，去除光致抗蚀剂图案和抗反射涂层。 随后，执行SAC蚀刻工艺以使用硬掩模作为蚀刻掩模蚀刻层间绝缘层，从而获得暴露出设置在导电结构之间的蚀刻停止层的接触孔。 通过使用橡皮布回蚀工艺去除暴露的蚀刻停止层，此后施加清洁工艺。