公开(公告)号：US20100257429A1

公开(公告)日：2010-10-07

申请号：US12818709

申请日：2010-06-18

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C16/3427 ,  G06F11/1068 ,  G11C7/1006 ,  G11C8/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C19/00 ,  G11C29/00

摘要： A data memory system is provided which includes a nonvolatile memory cell array, an error correction code generation circuit, an error correction code decoding circuit, and a first circuit. The nonvolatile memory cell array includes a plurality of memory cells which store digital data each having at least a value of “1” or “0” as a charge of a charge accumulation layer included in each memory cell, and use a difference between charges of the accumulation layer as a writing bit or an erasing bit. The nonvolatile memory cell array erases memory cells in units of pages, each page being formed of adjacent memory cells included in the plurality of memory cells.

摘要翻译： 提供一种包括非易失性存储单元阵列，纠错码产生电路，纠错码解码电路和第一电路的数据存储系统。 非易失性存储单元阵列包括多个存储单元，其存储每个至少具有值“1”或“0”的数字数据作为每个存储单元中包含的电荷累积层的电荷，并且使用 作为写入位或擦除位的累加层。 非易失性存储单元阵列以页为单位擦除存储单元，每页由包含在多个存储单元中的相邻存储单元形成。

公开(公告)号：US07721239B2

公开(公告)日：2010-05-18

申请号：US11624386

申请日：2007-01-18

申请人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi ,  Toshiki Hisada

发明人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi ,  Toshiki Hisada

IPC分类号： G06F17/50

CPC分类号： G11C16/0483 ,  G11C16/08 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11529

摘要： A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting lines. One end side of the conductive lines sequentially departs from an end of the cell array when heading from one of the conductive lines to another one, the contact holes are arranged at one end side of the conductive lines, and size of the contact holes is larger than width of the conductive lines.

摘要翻译： 根据本发明的半导体集成电路包括由元件构成的单元阵列，具有布置在单元阵列上的线和空间的图案的导线，形成在导线上方的连接线，以及将导线 到连接线。 导线的一端侧从导体线之一顺序离开电池阵列的端部，接触孔布置在导线的一端侧，接触孔的尺寸较大 比导线的宽度大。

公开(公告)号：US20100084703A1

公开(公告)日：2010-04-08

申请号：US12634406

申请日：2009-12-09

申请人： Daisuke TSURUMI ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

发明人： Daisuke TSURUMI ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

摘要翻译： 半导体存储器件包括源极区，漏极区，沟道区，电荷存储层和控制栅电极。 源极区域和漏极区域在半导体衬底的表面中彼此分开地形成。 沟道区形成在半导体衬底中并位于源极区和漏极区之间。 电荷存储层形成在通道区域上，其间插入有第一绝缘膜。 控制栅极电极形成在电荷存储层上，其间插入有第二绝缘膜。 控制门具有以5nm或更大的曲率半径圆化的上角部。

公开(公告)号：US07569898B2

公开(公告)日：2009-08-04

申请号：US11671229

申请日：2007-02-05

申请人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi

发明人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi

IPC分类号： H01L27/088

CPC分类号： H01L21/823807 ,  H01L21/823857 ,  H01L21/823892

摘要： A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks.

摘要翻译： 根据本发明的实施例的半导体器件包括第一导电类型的第一半导体区域，形成在第一半导体区域中的第二导电类型的第一MIS晶体管，第二导电类型的第二半导体区域，以及 形成在第二半导体区域中的第一导电类型的第二MIS晶体管。 第一MIS晶体管的第一栅极绝缘层比第二MIS晶体管的第二栅极绝缘层厚，并且第二MIS晶体管的沟道区中的第一导电类型的杂质的轮廓具有峰值。

公开(公告)号：US20090146701A1

公开(公告)日：2009-06-11

申请号：US12326482

申请日：2008-12-02

申请人： Mitsuhiro NOGUCHI ,  Kenji GOMIKAWA

发明人： Mitsuhiro NOGUCHI ,  Kenji GOMIKAWA

IPC分类号： H03L7/00 ,  H01L29/94 ,  H01L29/792

CPC分类号： G11C16/24 ,  G11C16/30 ,  H01L27/0207 ,  H01L27/0222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

摘要翻译： 半导体器件包括MOS晶体管，电容器元件，电压产生电路，接触插头和存储单元。 MOS晶体管和电容器元件分别形成在第一元件区域和第二元件区域中。 在电压产生电路中，MOS晶体管的电流路径串联连接，并且电容器元件连接到MOS晶体管的源极或漏极。 接触插塞形成在源极或漏极上，以连接MOS晶体管或MOS晶体管之一以及电容器元件之一。 位于串联连接的最后级的MOS晶体管的栅极和接触插塞之间的距离大于串联连接中位于初始阶段的第二个MOS晶体管的距离。

公开(公告)号：US20090003070A1

公开(公告)日：2009-01-01

申请号：US11869160

申请日：2007-10-09

申请人： Kenji Gomikawa ,  Kenji Sawamura ,  Mitsuhiro Noguchi

发明人： Kenji Gomikawa ,  Kenji Sawamura ,  Mitsuhiro Noguchi

IPC分类号： G11C11/34 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336

摘要： A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string.

摘要翻译： 半导体存储器件包括设置在半导体衬底上的存储单元串和包括栅极绝缘膜的第一选择晶体管，该第一选择晶体管包括栅极绝缘膜，该第一选择晶体管设置在半导体衬底上，该半导体衬底的中心部分具有较低的凹部结构， 设置有存储单元串的半导体衬底和设置在栅极绝缘膜上的栅电极，第一选择晶体管选择存储单元串。

公开(公告)号：US07420259B2

公开(公告)日：2008-09-02

申请号：US11373982

申请日：2006-03-14

申请人： Seiichi Mori ,  Mitsuhiro Noguchi

发明人： Seiichi Mori ,  Mitsuhiro Noguchi

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/42336

摘要： A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.

摘要翻译： 第一绝缘膜，第一导体膜和盖依次形成在半导体基板上。 以相同的图案蚀刻第一绝缘膜，第一导体膜和盖以及基板。 第二绝缘膜被放置在该蚀刻图案中。 盖子被移除。 第二导体膜形成在第二绝缘膜的侧面上。

公开(公告)号：US07402475B2

公开(公告)日：2008-07-22

申请号：US11265292

申请日：2005-11-03

申请人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

发明人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

摘要翻译： 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

公开(公告)号：US20080116503A1

公开(公告)日：2008-05-22

申请号：US11940838

申请日：2007-11-15

申请人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

发明人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

摘要翻译： 半导体存储器件包括源极区，漏极区，沟道区，电荷存储层和控制栅电极。 源极区域和漏极区域在半导体衬底的表面中彼此分开地形成。 沟道区形成在半导体衬底中并位于源极区和漏极区之间。 电荷存储层形成在通道区域上，其间插入有第一绝缘膜。 控制栅极电极形成在电荷存储层上，其间插入有第二绝缘膜。 控制门具有以5nm或更大的曲率半径圆化的上角部。

公开(公告)号：US20070215958A1

公开(公告)日：2007-09-20

申请号：US11798593

申请日：2007-05-15

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L29/94

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。