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    High Capacity Low Cost Multi-State Magnetic Memory
    72.
    发明申请
    High Capacity Low Cost Multi-State Magnetic Memory 审中-公开
    大容量低成本多态磁存储器

    公开(公告)号：US20080246104A1

    公开(公告)日：2008-10-09

    申请号：US11866830

    申请日：2007-10-03

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: H01L29/82

    CPC classification number: G11C11/5607 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    Abstract: One embodiment of the present invention includes multi-state current-switching magnetic memory element including a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states.

    Abstract translation: 本发明的一个实施例包括多状态电流切换磁存储元件，其包括两个或多个磁隧道结（MTJ）的堆叠，每个MTJ具有自由层，并且通过形成的晶种层与堆叠中的其它MTJ分离 在隔离层上，用于存储多于一位的信息的堆栈，其中施加到存储器元件的不同电平的电流导致切换到不同的状态。

    LOW RESISTANCE HIGH-TMR MAGNETIC TUNNEL JUNCTION AND PROCESS FOR FABRICATION THEREOF
    74.
    发明申请
    LOW RESISTANCE HIGH-TMR MAGNETIC TUNNEL JUNCTION AND PROCESS FOR FABRICATION THEREOF 有权
    低电阻高磁铁隧道结及其制造方法

    公开(公告)号：US20080164548A1

    公开(公告)日：2008-07-10

    申请号：US12040801

    申请日：2008-02-29

    Applicant: Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Roger Klas MALMHALL

    Inventor： Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Roger Klas MALMHALL

    IPC: H01L29/82 ,  H01L21/00

    CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  H01L43/08

    Abstract: One embodiment of the present invention includes a non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.

    Abstract translation: 本发明的一个实施例包括非易失性磁存储元件，其包括固定层，形成在固定层顶部上的阻挡层和形成在阻挡层顶部上的自由层，其中势垒层的电阻率 通过将所述阻挡层置于压应力下来减少。 或者通过使用压缩应力诱导层或在溅射过程中使用惰性气体在溅射过程中作为阻挡层被沉积或通过将压应力诱导分子引入到阻挡层的分子晶格中而引起压缩应力。

    NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY
    75.
    发明申请
    NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY 有权
    基于非均匀开关的非易失性磁性存储器

    公开(公告)号：US20080094886A1

    公开(公告)日：2008-04-24

    申请号：US11674124

    申请日：2007-02-12

    Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: G11C11/14 ,  H01L21/8239

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

    Abstract: One embodiment of the present invention includes a non-uniform switching based non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer, wherein switching current is applied, in a direction that is substantially perpendicular to the fixed, barrier, first free, non-uniform and the second free layers causing switching between states of the first, second free and non-uniform layers with substantially reduced switching current.

    Abstract translation: 本发明的一个实施例包括：非均匀的基于开关的非易失性磁存储元件，其包括固定层，形成在固定层顶部的阻挡层，形成在阻挡层顶部上的第一自由层， 形成在第一自由层的顶部上的均匀开关层（NSL）和形成在非均匀开关层顶部的第二自由层，其中施加开关电流，其基本上垂直于固定屏障的方向， 第一自由，不均匀和第二自由层引起第一，第二自由和非均匀层的状态之间的切换，其开关电流大大降低。

    Internal oscillator circuit including a ring oscillator controlled by a voltage regulator circuit
    77.
    发明授权
    Internal oscillator circuit including a ring oscillator controlled by a voltage regulator circuit 有权
    内部振荡器电路包括由稳压电路控制的环形振荡器

    公开(公告)号：US6084483A

    公开(公告)日：2000-07-04

    申请号：US265192

    申请日：1999-03-10

    Applicant: Parviz Keshtbod

    Inventor： Parviz Keshtbod

    IPC: H03K3/03 ,  H03B5/04

    CPC classification number: H03K3/0315

    Abstract: An oscillator circuit residing internally to a semiconductor device for generating a clock signal for use by digital circuits. The oscillator circuit includes a voltage regulator circuit responsive to frequency selection signals for selecting a predetermined frequency and a supply voltage. The voltage regulator circuit is operative to generate a voltage reference signal having a voltage level being adjusted to compensate for variations due to temperature, process and supply voltage variations. The oscillator circuit further includes a ring oscillator circuit responsive to the voltage reference signal for generating a clock out signal having a particular frequency based upon the voltage level of the voltage reference signal. Wherein the frequency of the clock out signal remains substantially constant despite temperature, process and supply voltage variations in the semiconductor circuit.

    Abstract translation: 位于半导体器件内部的振荡器电路，用于产生由数字电路使用的时钟信号。 振荡器电路包括响应于用于选择预定频率和电源电压的频率选择信号的电压调节器电路。 电压调节器电路用于产生电压参考信号，该电压参考信号的电压电平被调整以补偿由温度，过程和电源电压变化引起的变化。 振荡器电路还包括响应于电压参考信号的环形振荡器电路，用于基于电压参考信号的电压电平产生具有特定频率的时钟输出信号。 其中，尽管半导体电路中的温度，过程和电源电压变化，时钟输出信号的频率保持基本恒定。

    Spacer flash cell process
    78.
    发明授权
    Spacer flash cell process 失效
    间隔闪存单元过程

    公开(公告)号：US5640031A

    公开(公告)日：1997-06-17

    申请号：US413349

    申请日：1995-03-30

    Applicant: Parviz Keshtbod

    Inventor： Parviz Keshtbod

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a metal, preferably tungsten or a tungsten alloy. The field oxide is selectively removed. A gate oxide is grown and a first polysilicon layer is formed and then etched to form spacers along the edges of the metal/second insulator structure. The first polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A second polysilicon layer is formed over the tunneling insulator.

    Abstract translation: 闪存EPROM单元在编程期间通过在浮动栅极和位线之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将电子从Poly间隔物的尖端引导到控制栅极进行的。 单元被适配成使得阵列内的每个单元的源极是相邻单元的源极，漏极是另一相邻单元的漏极。 通过在优选为场氧化物的第一绝缘体中的开口将漏区形成为衬底而形成电池。 第二绝缘体沉积在第一绝缘体上方，在衬底上并且沿着开口的侧壁，并且优选地是薄层，使得开口被薄绝缘层覆盖。 绝缘开口填充有金属，优选钨或钨合金。 有选择地去除场氧化物。 生长栅极氧化物并形成第一多晶硅层，然后蚀刻以沿着金属/第二绝缘体结构的边缘形成间隔物。 选择性地蚀刻第一多晶硅，并在其上形成隧穿绝缘体层。 在隧道绝缘体上形成第二多晶硅层。

    Non-volatile memory system of multi-level transistor cells and methods using same
    79.
    发明授权
    Non-volatile memory system of multi-level transistor cells and methods using same 失效
    多级晶体管单元的非易失性存储器系统及其使用方法

    公开(公告)号：US5596526A

    公开(公告)日：1997-01-21

    申请号：US515188

    申请日：1995-08-15

    Applicant: Mahmud Assar ,  Parviz Keshtbod

    Inventor： Mahmud Assar ,  Parviz Keshtbod

    IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C11/34

    CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5642

    Abstract: A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

    Abstract translation: 多级NAND架构非易失性存储器件通过与恒定电流电平进行比较来读取和编程存储器单元，每个存储单元存储多于一位的数据，同时选择性地调整读或编程的单元或单元上的栅极电压。 提供多个读取和写入参考单元，每个编程为对应于多级编程中的每一个，其中在读取存储器单元期间，读取的参考单元提供恒定电流电平，并且在写入存储器单元期间，写入 参考细胞提供相同的。 此外，在读取操作期间，将相应的写入参考单元耦合到读取参考单元以测量与读取存储器单元相关联的读取时间。

    MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    80.
    发明申请
    MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM) 有权
    多端口磁力随机存取存储器（MRAM）

    公开(公告)号：US20140192590A1

    公开(公告)日：2014-07-10

    申请号：US14204274

    申请日：2014-03-11

    Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

    Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

    Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

    Abstract translation: 存储器阵列被组织成电阻元件的行和列，并且被公开为包括要读取或要写入的电阻元件。 此外，第一存取晶体管耦合到电阻元件和第一源极线，第二存取晶体管耦合到电阻元件和第二源极线，电阻元件在一端被耦合到第一和第二存取 晶体管和位线的相对端。 存储器阵列还具有各自耦合到位线的其它电阻元件。 在读取其中一个或多个其它电阻元件的同时写入电阻元件。

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