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    Nonvolatile memory using flexible erasing methods and method and system for using same
    3.
    发明授权
    Nonvolatile memory using flexible erasing methods and method and system for using same 有权
    非易失性存储器采用灵活的擦除方法和方法及系统使用

    公开(公告)号：US06411546B1

    公开(公告)日：2002-06-25

    申请号：US09565517

    申请日：2000-05-05

    Applicant: Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: G11C1604

    CPC classification number: G11C16/102 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G11C8/12 ,  G11C16/08

    Abstract: An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.

    Abstract translation: 公开了本发明的实施例，其包括用于控制对由行和列组成的非易失性存储器阵列执行的擦除操作的非易失性存储器系统，非易失性存储器阵列存储组织成块的数字信息，每个块具有一个或多个信息扇区 并且每个扇区具有用户数据字段和扩展字段，并且每个扇区存储在存储器阵列的行内。 控制器电路耦合到主机电路并且可操作以对非易失性存储器阵列执行擦除操作，控制器电路擦除所识别的具有特定用户数据字段和特定扩展字段的信息扇区，其中特定用户字段和特定用户字段 扩展字段被分别擦除。

    Non-uniform switching based non-volatile magnetic based memory
    5.
    发明授权
    Non-uniform switching based non-volatile magnetic based memory 有权
    基于非均匀开关的非易失性磁性存储器

    公开(公告)号：US08389301B2

    公开(公告)日：2013-03-05

    申请号：US13305668

    申请日：2011-11-28

    Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: H01L21/00

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

    Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.

    Abstract translation: 非均匀开关型非易失性磁存储元件包括固定层，形成在固定层顶部上的阻挡层，形成在阻挡层顶部上的第一自由层，形成非均匀开关层（NSL） 在第一自由层的顶部和形成在不均匀开关层的顶部上的第二自由层。 在基本上垂直于固定层，阻挡层，第一自由层，不均匀的开关层和第二自由层的方向上施加开关电流，导致第一自由层，第二自由层和非自由层的状态之间的切换， 均匀的开关层，开关电流大大降低。

    LOW-COST NON-VOLATILE FLASH-RAM MEMORY
    6.
    发明申请
    LOW-COST NON-VOLATILE FLASH-RAM MEMORY 有权
    低成本非易失性闪存存储器

    公开(公告)号：US20120170361A1

    公开(公告)日：2012-07-05

    申请号：US13345600

    申请日：2012-01-06

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud ASSAR

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud ASSAR

    IPC: G11C11/14

    CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

    Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

    Abstract translation: 闪存RAM存储器包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器， 易失性RAM驻留在单片模具上。 非易失性RAM由以三维形式布置的磁存储单元堆叠形成，用于更高密度和更低成本。

    NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY
    7.
    发明申请
    NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY 有权
    基于非均匀开关的非易失性磁性存储器

    公开(公告)号：US20080094886A1

    公开(公告)日：2008-04-24

    申请号：US11674124

    申请日：2007-02-12

    Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: G11C11/14 ,  H01L21/8239

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

    Abstract: One embodiment of the present invention includes a non-uniform switching based non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer, wherein switching current is applied, in a direction that is substantially perpendicular to the fixed, barrier, first free, non-uniform and the second free layers causing switching between states of the first, second free and non-uniform layers with substantially reduced switching current.

    Abstract translation: 本发明的一个实施例包括：非均匀的基于开关的非易失性磁存储元件，其包括固定层，形成在固定层顶部的阻挡层，形成在阻挡层顶部上的第一自由层， 形成在第一自由层的顶部上的均匀开关层（NSL）和形成在非均匀开关层顶部的第二自由层，其中施加开关电流，其基本上垂直于固定屏障的方向， 第一自由，不均匀和第二自由层引起第一，第二自由和非均匀层的状态之间的切换，其开关电流大大降低。

    Non-volatile memory system of multi-level transistor cells and methods using same
    9.
    发明授权
    Non-volatile memory system of multi-level transistor cells and methods using same 失效
    多级晶体管单元的非易失性存储器系统及其使用方法

    公开(公告)号：US5596526A

    公开(公告)日：1997-01-21

    申请号：US515188

    申请日：1995-08-15

    Applicant: Mahmud Assar ,  Parviz Keshtbod

    Inventor： Mahmud Assar ,  Parviz Keshtbod

    IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C11/34

    CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5642

    Abstract: A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

    Abstract translation: 多级NAND架构非易失性存储器件通过与恒定电流电平进行比较来读取和编程存储器单元，每个存储单元存储多于一位的数据，同时选择性地调整读或编程的单元或单元上的栅极电压。 提供多个读取和写入参考单元，每个编程为对应于多级编程中的每一个，其中在读取存储器单元期间，读取的参考单元提供恒定电流电平，并且在写入存储器单元期间，写入 参考细胞提供相同的。 此外，在读取操作期间，将相应的写入参考单元耦合到读取参考单元以测量与读取存储器单元相关联的读取时间。

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