Abstract:
A method of chemical mechanical polishing a metal layer on a substrate in which the substrate is polished at a first polishing rate. Polishing is monitored with an eddy current monitoring system, and the polishing rate is reduced to a second polishing rate when the eddy current monitoring system indicates that a predetermined thickness of the metal layer remains on the substrate. Then polishing is monitored with an optical monitoring system, and polishing is halted when the optical monitoring system indicates that an underlying layer is at least partially exposed.
Abstract:
Method and apparatus are provided for polishing substrates comprising conductive and low k dielectric materials with reduced or minimum substrate surface damage and delamination. In one aspect, a method is provided for processing a substrate including positioning a substrate having a conductive material formed thereon in a polishing apparatus having one or more rotational carrier heads and one or more rotatable platens, wherein the carrier head comprises a retaining ring and a membrane for securing a substrate and the platen has a polishing article disposed thereon, contacting the substrate surface and the polishing article to each other at a retaining ring contact pressure of about 0.4 psi or greater than a membrane pressure, and polishing the substrate to remove conductive material.
Abstract:
Dishing in chemical mechanical polishing (CMP) is reduced by introducing a material that balances electrochemical forces. In a first embodiment of the invention, a polishing pad having copper material in grooves on the polishing pad surface is used in the polishing process to reduce dishing. In a second embodiment of the invention, the polishing pad has perforations with copper fillings. In a third embodiment of the invention, a copper retaining ring on the polishing head introduces copper material to the CMP process to reduce dishing. In a fourth embodiment of the invention, a conditioning plate of copper is used in the polishing apparatus. In a fifth embodiment of the invention, additional copper features are placed on the substrate to be polished. The polishing of the additional features introduces copper steadily through the polishing process. In a sixth embodiment of the invention, copper compounds are added to the polish slurry.
Abstract:
A CMP slurry is formulated with an oxidizer capable of oxidizing a metal undergoing planarization and yielding a complexing agent which complexes with the oxidized metal thereby minimizing overetching. The slurry may further include abrasive particles, inhibitors, pH adjusting agents, and combinations thereof.
Abstract:
Cu metallization is treated to reduce defects and effect passivation, and to reduce leakage between lines, by removing surface defects subsequent to CMP and barrier layer removal. Embodiments include the sequential steps of: CMP and barrier layer removal; buffing with a solution comprising citric acid, ammonium hydroxide and deionized water to remove copper oxide; rinsing with deionized water or an inhibitor solution, e.g., benzotriazole or 5-methyl triazole in deionized water; buffing with an abrasive slurry; and rinsing with deionized water or an inhibitor solution.
Abstract:
A selective Damascene chemical mechanical polishing (CMP) technique is used to planarize a semiconductor device to remove surface topography. The semiconductor device includes a semiconductor layer formed on a substrate, an insulating layer formed over the semiconductor layer and patterned to expose a portion of the semiconductor layer, a barrier layer formed over the insulating layer and the exposed portion of the semiconductor layer, and an electrically conductive layer formed over the barrier layer. The semiconductor device is pressed against a first rotating polishing pad that has no embedded abrasive particles to remove a portion of the conductive layer that overlies both the barrier layer and the insulating layer. The semiconductor device is then pressed against a second rotating polishing pad that has embedded abrasive particles to expose a portion of the barrier layer that overlies the insulating layer. The device is then pressed against a third rotating polishing pad that has no embedded abrasive particles to remove the portion of the barrier layer that overlies the insulating layer.
Abstract:
A method of chemical mechanical planarization of a semiconductor device provides a semiconductor device having a device front surface and a device back surface with the device front surface being a top surface of a second metal layer. A first planarizing step planarizes the device front surface with a first medium to expose a device second front surface, where the first medium comprises a first abrasive component and a first chemical solution. A rinsing step then rinses the device back surface with water. A second planarizing step then planarizes the device second front surface with a second medium where the second medium comprises a second abrasive component and a second chemical solution.
Abstract:
A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different source containers (111 and 112), wherein the first slurry is dispensed until the tungsten is removed and then the slurry dispense is switched to the second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.
Abstract:
A chemical mechanical polishing (CMP) method utilizes a polishing pad (21) and an under pad (20). The under pad (20) has an edge portion (24) and a central portion (22). The central portion (22) has either a shore D hardness less than a shore D hardness of the portion (24), greater slurry absorption than the edge portion (24), or more compressibility than the edge portion (24). This composite material under pad (20) will improve polishing uniformity of a semiconductor wafer (39). In addition, the use of the polishing pads (20 and 21) allows for greater final wafer profile control than was previously available in the art (FIGS. 4-6).