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    Programmable logic device architecture for accommodating specialized circuitry
    71.
    发明申请
    Programmable logic device architecture for accommodating specialized circuitry 失效
    用于容纳专用电路的可编程逻辑器件架构

    公开(公告)号：US20070063733A1

    公开(公告)日：2007-03-22

    申请号：US11230002

    申请日：2005-09-19

    申请人： Sergey Shumarayev ,  Rakesh Patel ,  Chong Lee

    发明人： Sergey Shumarayev ,  Rakesh Patel ,  Chong Lee

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17704 ,  H03K19/17732 ,  H03K19/17744

    摘要： A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized circuitry. The peripheral specialized regions, which are not connected to the remainder of the programmable logic device (and may be made on separate dies from the remainder of the programmable logic device mounted on a common substrate), and one or both of the programmable logic regions and the conventional I/O regions, have contacts for metallization traces or other interconnections to connect the peripheral specialized regions to the remainder of the programmable logic device. The same PLD can be sold with or without the specialized circuitry capability by providing or not providing the interconnections. The peripheral specialized regions may include high-speed I/O (basic, up to about 3 Gbps, and enhanced, up to about 10-12 Gbps), as well as other types of specialized circuitry.

    摘要翻译： 具有一个或多个可编程逻辑区域和一个或多个常规输入/输出区域的可编程逻辑器件（PLD）还具有包括专用电路的一个或多个外围区域。 外围专用区域不连接到可编程逻辑器件的其余部分（并且可以在与安装在公共衬底上的可编程逻辑器件的其余部分分开的管芯上）制造，以及一个或两个可编程逻辑区域 常规I / O区域具有用于金属化迹线或其它互连的触点，以将外围专用区域连接到可编程逻辑器件的其余部分。 通过提供或不提供互连，可以在具有或不具有专用电路能力的情况下出售相同的PLD。 外围专业区域可能包括高速I / O（基本，高达约3 Gbps，增强，高达10-12 Gbps）以及其他类型的专用电路。

    Clock circuitry for programmable logic devices
    72.
    发明申请
    Clock circuitry for programmable logic devices 有权

    公开(公告)号：US20070019766A1

    公开(公告)日：2007-01-25

    申请号：US11432419

    申请日：2006-05-10

    申请人： William Bereza ,  Shoujun Wang ,  Rakesh Patel

    发明人： William Bereza ,  Shoujun Wang ,  Rakesh Patel

    IPC分类号： H04L7/00

    CPC分类号： H03L7/07 ,  H03K19/1774 ,  H03K19/17744 ,  H03M9/00

    摘要： Data transmitter circuitry on a programmable logic device (“PLD”) includes a plurality of channels of serializer circuitry, and a plurality of clock multiplier units (“CMUs”), each of which is associated with a respective subplurality of the serializer channels. Each CMU includes multiple reference clock signal sources, multiple phase-locked loop (“PLL”) circuits, and circuitry for allowing any PLL to get its reference input from any of the reference sources. Raw and centrally processed clock signals produced by each CMU are distributed to the serializer channels associated with that CMU and, at least in the case of the centrally processed signals, to the serializer channels associated with another CMU. The signal that controls release of parallel data to each serializer channel can be an output signal of that channel, or it can be an output signal of any CMU from which that channel can get a clock signal.

    Apparatus and methods for programmable slew rate control in transmitter circuits
    73.
    发明申请
    Apparatus and methods for programmable slew rate control in transmitter circuits 审中-公开
    发射机电路中可编程转换速率控制的装置和方法

    公开(公告)号：US20070013411A1

    公开(公告)日：2007-01-18

    申请号：US11183288

    申请日：2005-07-14

    申请人： Kazi Asaduzzaman ,  Sergey Shumarayev ,  Thungoc Tran ,  Wilson Wong ,  Rakesh Patel

    发明人： Kazi Asaduzzaman ,  Sergey Shumarayev ,  Thungoc Tran ,  Wilson Wong ,  Rakesh Patel

    IPC分类号： H03K19/094

    CPC分类号： H03K17/164

    摘要： High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the driver input. The driver and/or pre-driver circuits may include transistors with variable drive strengths. The driver and/or pre-driver circuits may also include selectably enabled stages for varying the circuit drive strength. The pre-driver circuitry may be delay matched to maintain signal quality. Other circuitry and methods are also described.

    摘要翻译： 可能需要高速变送器驱动器和其他类型的驱动电路来产生具有可变转换速率的输出信号。 描述了用于提供可变转换速率控制的驱动电路和方法。 可以使用具有可变转换速率的前驱动器电路在驱动器输入端提供具有可变转换速率的信号。 驱动器和/或预驱动器电路可以包括具有可变驱动强度的晶体管。 驱动器和/或预驱动器电路还可以包括用于改变电路驱动强度的可选择地启用的级。 预驱动器电路可以被延迟匹配以保持信号质量。 还描述了其它电路和方法。

    Data converter with multiple conversions for padded-protocol interface
    74.
    发明授权
    Data converter with multiple conversions for padded-protocol interface 有权
    具有多个转换的数据转换器，用于填充协议接口

    公开(公告)号：US07151470B1

    公开(公告)日：2006-12-19

    申请号：US10969450

    申请日：2004-10-20

    申请人： Ning Xue ,  Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

    发明人： Ning Xue ,  Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

    IPC分类号： H03M7/00

    CPC分类号： H03M7/04

    摘要： A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.

    摘要翻译： 用于填充协议接口的数据转换器或“变速箱”可以执行多个不同的转换，例如在64位和66位之间，在24位和26位之间，或在48位和50位之间。 这是通过使用可允许用户选择时钟速度的可编程分频器从不同时钟速度对齿轮箱进行计时的，这些时钟速度全部来自相同的主时钟（可以从接收机实施例中的数据恢复）。 当转换不是设计齿轮箱的最大宽度的转换时，未使用的位将被忽略。 转换器还可以在不同宽度的数据中找到用于对齐目的的填充位，当数据不是设计转换器的最宽时，再次忽略未使用的位。

    Multiple data rates in programmable logic device serial interface
    75.
    发明申请
    Multiple data rates in programmable logic device serial interface 失效

    公开(公告)号：US20060233172A1

    公开(公告)日：2006-10-19

    申请号：US11177034

    申请日：2005-07-08

    申请人： Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

    发明人： Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

    IPC分类号： H04L12/28

    CPC分类号： H03K19/17744

    摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

    Methods and apparatus to DC couple LVDS driver to CML levels
    76.
    发明申请
    Methods and apparatus to DC couple LVDS driver to CML levels 有权
    将LVDS驱动程序直接耦合到CML级别的方法和设备

    公开(公告)号：US20060220681A1

    公开(公告)日：2006-10-05

    申请号：US11098832

    申请日：2005-04-04

    申请人： Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

    发明人： Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

    IPC分类号： H03K19/094

    CPC分类号： H03K19/017545

    摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.

    摘要翻译： 为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。 将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。 此外，电阻下拉可以是可编程的。 这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

    Multiple data rates in programmable logic device serial interface
    79.
    发明授权
    Multiple data rates in programmable logic device serial interface 有权
    可编程逻辑器件串行接口中的多个数据速率

    公开(公告)号：US06888376B1

    公开(公告)日：2005-05-03

    申请号：US10670845

    申请日：2003-09-24

    申请人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

    发明人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/1778 ,  H03K19/17796

    摘要： A serial interface for a programmable logic device supports a higher physical medium attachment (“PMA”) data rate than the available physical coding sublayer (“PCS”) data rate by using multiple PCS modules, operating in parallel, to support one PMA module. In a channel-based structure, the PMA module is supported by a PCS module in its own channel and at least one PCS module from a second channel. The second channel may include its own PMA module which, if provided, may operate at a lower rate, supportable by the PCS module in that channel. Optionally, two modes are provided. In one mode, two PCS modules in two channels support one higher-speed PMA module in one of the channels. In a second mode, each PCS module supports a PMA module in its own channel, with the higher-speed PMA module constrained to operate at the lower data rate of the PCS module.

    摘要翻译： 用于可编程逻辑器件的串行接口通过使用并行操作的多个PCS模块来支持比可用物理编码子层（“PCS”）数据速率更高的物理介质附加（“PMA”）数据速率，以支持一个PMA模块。 在基于通道的结构中，PMA模块由其自身通道中的PCS模块和来自第二通道的至少一个PCS模块支持。 第二通道可以包括其自己的PMA模块，如果提供的话，该模块可以以较低的速率操作，由PCS模块在该通道中支持。 可选地，提供两种模式。 在一种模式下，两个通道中的两个PCS模块在其中一个通道中支持一个更高速的PMA模块。 在第二种模式下，每个PCS模块都支持自己的通道中的PMA模块，而高速PMA模块则被限制在PCS模块的较低数据速率下工作。