公开(公告)号：US20240387328A1

公开(公告)日：2024-11-21

申请号：US18319132

申请日：2023-05-17

Applicant: STMicroelectronics International N.V.

Inventor： Pascal Fornara ,  Antonin Chollet ,  Julien Amouroux

IPC: H01L23/48 ,  H01L21/764 ,  H01L21/768 ,  H01L29/06

Abstract: A method for manufacturing a semiconductor device includes depositing a first protective layer over a first conductive feature and a second conductive feature. The first protective layer covers respective sidewalls and top surfaces of the first conductive feature and the second conductive feature. A portion of the first protective layer between the first conductive feature and the second conductive feature is removed. After removing the portion of the first protective layer, an intermetal dielectric layer is formed between the first conductive feature and the second conductive feature.

公开(公告)号：US12149241B2

公开(公告)日：2024-11-19

申请号：US18334989

申请日：2023-06-14

Applicant: STMicroelectronics International N.V.

Inventor： Vaibhav Garg ,  Abhishek Jain ,  Anand Kumar

IPC: H03K17/693 ,  H03K17/687 ,  H03K19/017

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

公开(公告)号：US20240377198A1

公开(公告)日：2024-11-14

申请号：US18654869

申请日：2024-05-03

Applicant: STMicroelectronics International N.V.

Inventor： Gabriele GATTERE ,  Luca GUERINONI

IPC: G01C19/5762 ,  G01C19/5726

Abstract: Test method of a vibrational MEMS structure wherein, a direct, variable modification voltage is applied to a resonance modification test structure having non-rectilinear electrodes, modifying the resonance frequency of the movable mass and the driving frequency. During the test, the movable mass is verified about stability and, if not stable, the vibrational MEMS structure is rejected.

公开(公告)号：US20240370382A1

公开(公告)日：2024-11-07

申请号：US18652555

申请日：2024-05-01

Applicant: STMicroelectronics International N.V.

Inventor： Loic Pallardy ,  Vincent Berthelot

IPC: G06F12/14

Abstract: The system on chip includes a memory controller adapted to receive transactions containing transaction information defining an access to a memory, the memory controller being configured to store the transaction information in a command register, and to control the access to the memory from the content of the command register. The memory controller includes verification circuitry configured to determine the access to the memory depending on a comparison between the transaction information stored in the command register and a list of special information defining special transactions.

公开(公告)号：US20240367610A1

公开(公告)日：2024-11-07

申请号：US18774290

申请日：2024-07-16

Applicant: STMicroelectronics International N.V.

Inventor： Subodh Vikram SHUKLA ,  Saurabh SONA

IPC: B60R25/04 ,  G06F21/44 ,  G06F21/60 ,  H02P27/06 ,  H03K17/94 ,  H04B10/80

Abstract: A method of performing an authentication process to authenticate an electric motor unit includes establishing, by an external controller, secure encrypted communication with motor electronics of the electric motor unit, and sending, by the external controller, an authentication request to the motor electronics over the secure encrypted communication. The method further includes receiving, by the external controller, an authentication response from the motor electronics, verifying, by the external controller, a motor of the electronic motor unit as an authorized part based on the authentication response, and enabling control of the motor by the external controller only after successful authentication.

公开(公告)号：US12136917B2

公开(公告)日：2024-11-05

申请号：US18151337

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Kallol Chatterjee ,  Rohit Kumar Gupta

IPC: H03K19/0185

Abstract: Provided is a voltage level shifter that operates in sub-threshold voltages. The level shifter includes a level shifting stage. The level shifting stage receives a first signal from a first voltage domain and outputs a second signal to a second voltage domain. The level shifter includes a first auxiliary stage. In response to the first signal having a first voltage level corresponding to a first logical state and a first node of the level shifting stage having a supply voltage level, the first auxiliary stage sources current to a second node of the level shifting stage. Sourcing the current to the second node accelerates a transition of the first node to a reference voltage. The level shifting stage outputs a second signal to a second voltage domain.

公开(公告)号：US20240363584A1

公开(公告)日：2024-10-31

申请号：US18637865

申请日：2024-04-17

Applicant: STMicroelectronics International N.V.

Inventor： Antonio BELLIZZI ,  Nicoletta MODARELLI

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L24/48 ,  H01L2224/48175 ,  H01L2224/97

Abstract: Semiconductor dice are arranged onto a first surface of a common electrically conductive substrate. The common electrically conductive substrate has a second surface opposite the first surface and includes substrate portions and elongated sacrificial connecting bars extending between adjacent substrate portions. Insulating material is coated on the second surface of the elongate sacrificial connecting bars. Solder material is grown on the second surface of the common electrically conductive substrate. The insulating material counters growth of the solder material on the second surface of the elongate sacrificial connecting bars. Singulated individual semiconductor devices are provided by cutting the common electrically conductive substrate along the length of the elongate sacrificial connecting bars having the insulating material coated on its second surface.

公开(公告)号：US20240363187A1

公开(公告)日：2024-10-31

申请号：US18635569

申请日：2024-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Christophe LECOCQ ,  Yagnesh Dineshbhai VADERIYA ,  Anuj DHILLON ,  Cedric ESCALLIER ,  Harsh RAWAT ,  Kedar Janardan DHORI

IPC: G11C29/46 ,  G11C29/02 ,  G11C29/32

CPC classification number: G11C29/46 ,  G11C29/022 ,  G11C29/32 ,  G11C2029/3202

Abstract: A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.

公开(公告)号：US20240361791A1

公开(公告)日：2024-10-31

申请号：US18139786

申请日：2023-04-26

Applicant: STMicroelectronics International N.V.

Inventor： Federico MUSARRA ,  Sandor PETENYI

IPC: G05F1/575 ,  G05F1/565 ,  G05F3/24

CPC classification number: G05F1/575 ,  G05F1/565 ,  G05F3/24

Abstract: An electronic device includes multiple integrated circuits, each containing a power transistor connected between an input voltage node and a load node, as well as a regulation circuit generating at least one sense current representing the output current of the power transistor. The regulation circuits modulate the output currents of their power transistors based on a value derived from the sense currents generated by the regulation circuits of other integrated circuits. This derived value can be based on an average of the sense currents generated by the regulation circuits or on one of the sense currents. In particular, the integrated circuits can be arranged in a daisy-chained relationship, allowing each regulation circuit to compare its sense current with the one from the immediately preceding circuit, except for the first regulation circuit, which compares its sense current with the last circuit's sense current in the chain.

公开(公告)号：US20240356784A1

公开(公告)日：2024-10-24

申请号：US18639419

申请日：2024-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Nicolas Moeneclaey ,  Gilles Troussel ,  Christophe Tourniol

IPC: H04L25/02 ,  H04L12/40

CPC classification number: H04L25/026 ,  H04L12/40013 ,  H04L25/0272 ,  H04L25/0292 ,  H04L2012/40215

Abstract: The present disclosure relates to device including first and second terminals connected to a bus, third and fourth terminals connected to power supply and reference potentials. A first transistor and a first resistor are in series between the first terminal and a first diode connected to the third terminal. A second resistor, a second transistor and a second diode are in series between the first and fourth terminals. A third transistor and a third resistor are in series between the first diode and the second terminal. A fourth resistor, a fourth transistor and a third diode are in series between the second and fourth terminals. At each consecutive transmission of a dominant bit and of a recessive bit, a circuit sets the transistors at the ON state during a time period starting with the recessive bit.