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    Magnetoresistive asymmetry compensation
    71.
    发明授权
    Magnetoresistive asymmetry compensation 有权

    公开(公告)号：US11658669B2

    公开(公告)日：2023-05-23

    申请号：US17582376

    申请日：2022-01-24

    Applicant: Seagate Technology LLC

    Inventor： Jason Bellorado ,  Marcus Marrow ,  Zheng Wu

    IPC: G11B20/10 ,  G11B5/00 ,  H03M1/06 ,  H03G3/30 ,  G11B5/027 ,  G11B5/012

    CPC classification number: H03M1/06 ,  G11B5/012 ,  G11B5/027 ,  G11B20/10324 ,  H03G3/30 ,  H03G2201/103

    Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

    Hybrid storage device with three-level memory mapping
    75.
    发明授权
    Hybrid storage device with three-level memory mapping 有权

    公开(公告)号：US11630779B2

    公开(公告)日：2023-04-18

    申请号：US17528977

    申请日：2021-11-17

    Applicant: Seagate Technology LLC

    Inventor： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

    IPC: G06F12/0873 ,  G06F12/128 ,  G06F12/02

    Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

    Intelligent region utilization in a data storage device
    77.
    发明授权
    Intelligent region utilization in a data storage device 有权

    公开(公告)号：US11610603B2

    公开(公告)日：2023-03-21

    申请号：US17301433

    申请日：2021-04-02

    Applicant: Seagate Technology LLC

    Inventor： Chee Hou Peng ,  Ajay Narayan Kulkarni ,  Harry Tiotantra ,  KayHee Tang ,  WenXiang Xie

    IPC: G11B5/55 ,  G06F3/06 ,  G11B20/12 ,  G11B20/10

    Abstract: A data storage device can have one or more rotating data media with data tracks that are radially disposed from a central spindle. The data tracks may be logically divided into multiple regions while a write strategy is generated with a region module to set a sequence of different regions for future data writes. Receipt of a data write request to the data storage media from a host can prompt the region module to classify the data write request as a sequential or random write in order to intelligently select a region to satisfy the data write request based on the write strategy to maximize data writing consistency for data associated with the data write request.

    Garbage collection command scheduling
    80.
    发明授权
    Garbage collection command scheduling 有权

    公开(公告)号：US11593262B1

    公开(公告)日：2023-02-28

    申请号：US15962993

    申请日：2018-04-25

    Applicant: Seagate Technology LLC

    Inventor： Jonathan Henze ,  Michael Scott Hicken

    IPC: G06F12/02 ,  G06F3/06 ,  G06F16/17

    Abstract: Systems and methods are disclosed for the intelligent scheduling of garbage collection operations on a solid state memory. In certain embodiments, a method may comprise initiating a garbage collection process for a solid state memory (SSM) having a multiple die architecture, determining an order of die access for the garbage collection process based on an activity table indicating a use of one or more die in the multiple die architecture, and performing the garbage collection process based on the determined order of die access. Garbage collection reads may be directed to idle die to avoid conflicts with die busy performing other operations, thereby improving system performance.

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