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109 条记录 (耗时 0.075 秒)

    ELECTRICALLY PROGRAMMABLE FLOATING COMMON GATE CMOS DEVICE AND APPLICATIONS THEREOF
    71.
    发明申请
    ELECTRICALLY PROGRAMMABLE FLOATING COMMON GATE CMOS DEVICE AND APPLICATIONS THEREOF 有权
    电气可编程浮动通用门CMOS器件及其应用

    公开(公告)号：US20110292733A1

    公开(公告)日：2011-12-01

    申请号：US12786956

    申请日：2010-05-25

    申请人： Jin Cai ,  Tak H. Ning

    发明人： Jin Cai ,  Tak H. Ning

    IPC分类号： G11C16/04 ,  H01L27/088

    CPC分类号： H01L27/11521 ,  G11C16/0441 ,  H01L29/66825 ,  H01L29/7881

    摘要： A programmable CMOS device includes a PFET and an NFET that have a common floating gate. Depending on the configuration, the programmable CMOS device can be programmed, erased, and re-programmed repeatedly. The programming, erasure, and/or reprogramming can be effected by injection of electrons and/or holes into the floating gate. The programmable CMOS device can be employed as a fuse or an antifuse, to program a floating gate of another device, and/or to function as a latch. The programmable CMOS device can be formed employing standard logic compatible processes, i.e., without employing any additional processing steps.

    摘要翻译： 可编程CMOS器件包括具有公共浮动栅极的PFET和NFET。 根据配置，可重复编程，擦除和重新编程可编程CMOS器件。 编程，擦除和/或重新编程可以通过将电子和/或空穴注入浮动栅极来实现。 可编程CMOS器件可用作熔丝或反熔丝，以编程另一器件的浮置栅极和/或用作锁存器。 可编程CMOS器件可以使用标准逻辑兼容工艺形成，即不需要任何额外的处理步骤。

    SOI CMOS CIRCUITS WITH SUBSTRATE BIAS
    72.
    发明申请
    SOI CMOS CIRCUITS WITH SUBSTRATE BIAS 有权
    具有基极偏置的SOI CMOS电路

    公开(公告)号：US20090108355A1

    公开(公告)日：2009-04-30

    申请号：US12348391

    申请日：2009-01-05

    申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

    发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

    IPC分类号： H01L27/092

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

    摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.

    摘要翻译： 本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置 ）电路，其位于绝缘体上硅（SOI）衬底上。 具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。 例如，可以使用正衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负衬底偏置电压可以用于增加n-FET的阈值电压，但是 减少p-FET的电流。 此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

    Self-aligned bipolar transistor with inverted polycide base contact
    74.
    发明授权
    Self-aligned bipolar transistor with inverted polycide base contact 失效
    自对准双极晶体管与反向多晶硅基极接触

    公开(公告)号：US4495512A

    公开(公告)日：1985-01-22

    申请号：US385740

    申请日：1982-06-07

    申请人： Randall D. Isaac ,  Tak H. Ning

    发明人： Randall D. Isaac ,  Tak H. Ning

    IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L29/10 ,  H01L23/48 ,  H01L29/46 ,  H01L29/72

    CPC分类号： H01L29/66272 ,  H01L21/28518 ,  H01L29/1004 ,  Y10S148/035

    摘要： An inverted polycide extrinsic base contact serves as a diffusion source, yet still has low resistivity and is readily etchable down to silicon by techniques useful in manufacturing integrated circuits. The extrinsic base contact layer is made up of a metal silicide (e.g. WSi.sub.2) with an overlying doped polysilicon layer with coextensive apertures through doped polysilicon and metal silicide layers defining the emitter and intrinsic base region.The extrinsic base region is formed by diffusing boron impurities from the p.sup.+ polysilicon layer through the silicide layer. The silicide layer is of a metal silicide such as tungsten silicide (WSi.sub.2). The polysilicon layer acts as a diffusion source, since appropriate dopants (e.g., boron) diffuse rapidly through the metal silicide. Both the top surface of the p.sup.+ polysilicon layer and the sidewall edges of the polysilicon and silicide layers are covered by an insulating layer (e.g. SiO.sub.2) which also separates the emitter contact from the base contact layers.

    摘要翻译： 反向多硅化物非本征基极接触用作扩散源，但仍具有低电阻率，并且通过可用于制造集成电路的技术容易地向硅蚀刻。 外部基极接触层由金属硅化物（例如WSi2）与具有共同延伸孔的上覆掺杂多晶硅层组成，掺杂多晶硅和金属硅化物层限定发射极和本征基极区。 通过从p +多晶硅层通过硅化物层扩散硼杂质形成非本征基区。 硅化物层是诸如硅化钨（WSi2）之类的金属硅化物。 多晶硅层充当扩散源，因为合适的掺杂剂（例如硼）迅速扩散通过金属硅化物。 p +多晶硅层的顶表面和多晶硅和硅化物层的侧壁边缘都被绝缘层（例如SiO 2）覆盖，绝缘层也将发射极接触与基极接触层分开。

    Self-aligned semiconductor circuits and process therefor
    75.
    发明授权
    Self-aligned semiconductor circuits and process therefor 失效
    自对准半导体电路及其工艺

    公开(公告)号：US4338622A

    公开(公告)日：1982-07-06

    申请号：US53473

    申请日：1979-06-29

    申请人： George C. Feth ,  Tak H. Ning ,  Denny D. Tang ,  Siegfried K. Wiedmann ,  Hwa N. Yu

    发明人： George C. Feth ,  Tak H. Ning ,  Denny D. Tang ,  Siegfried K. Wiedmann ,  Hwa N. Yu

    IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/04

    CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L27/0233

    摘要： A semiconductor circuit in which a plurality of transistors is provided, the collector regions/contacts and the base regions/contacts of the transistors being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors of these transistors can be butted to a field oxide to reduce the extrinsic base area and to minimize excess charge storage in the base region. The base contacts, whether polysilicon or metal, etc. provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow. The use of a polysilicon layer for the base contacts, where "fingers" are provided by the polysilicon layer, enhances wirability and the mode of fabrication of the structure, since the polysilicon fingers can have an insulating layer (grown oxide) thereover to provide electrical isolation from over-lying conductors. These self-alignment techniques provide enhanced electrical properties since the distance between the base and collector contacts is minimized and since the base-emitter depletion layer capacitance, the stored charge and the base series resistance are reduced. From a processing standpoint, an additional masking step is not required to form the collector regions.

    摘要翻译： 提供多个晶体管的半导体电路，晶体管的集电极区域/触点和基极区域/触点相互自对准。 在一个实施例中，集电器具有导电层接触（例如金属）并且与多晶硅基底触点自对准，而在另一实施例中，基极触点由导电（金属）层组成，而多晶硅用于集电极触点。 这些晶体管的集电极可以对接到场氧化物以减少外部基极面积并且使基极区域中的过剩电荷存储最小化。 基极触点（无论是多晶硅还是金属）等提供交替的基极电流路径，使得外部基极面积的去除不会不利地影响可流过的基极电流的总量。 由于多晶硅指状物可以具有绝缘层（生长的氧化物）以提供电气，所以使用多晶硅层用于基底触点，其中“指状”由多晶硅层提供，从而提高了结构的布线性和制造方式， 与绝缘导体隔离。 这些自对准技术提供增强的电性能，因为基极和集电极触点之间的距离最小化，并且由于基极 - 发射极耗尽层电容，存储电荷和基极串联电阻减小。 从处理的观点来看，不需要附加的掩模步骤来形成收集区域。

    FET Containing stacked gates
    76.
    发明授权
    FET Containing stacked gates 失效
    包含堆叠栅极的FET

    公开(公告)号：US4282540A

    公开(公告)日：1981-08-04

    申请号：US86608

    申请日：1979-10-19

    申请人： Tak H. Ning ,  Carlton M. Osburn ,  Hwa N. Yu

    发明人： Tak H. Ning ,  Carlton M. Osburn ,  Hwa N. Yu

    IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788 ,  H01L29/78

    CPC分类号： H01L21/28273 ,  H01L21/033 ,  H01L29/4916 ,  H01L29/7881

    摘要： A field effect transistor (FET) comprising a floating gate and a control gate in a stacked relationship with each other and being self-aligned with each other and self-aligned with respect to source and drain regions. The fabrication technique employed comprises delineating both the floating gate and control gate in the same lithographic masking step.

    摘要翻译： 一种场效应晶体管（FET），其包括彼此堆叠关系的浮置栅极和控制栅极，并且彼此自对准并相对于源极和漏极区域自对准。 所采用的制造技术包括在相同的光刻掩模步骤中描绘浮动栅极和控制栅极。