公开(公告)号：US20060125121A1

公开(公告)日：2006-06-15

申请号：US11081416

申请日：2005-03-16

Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi ,  Chung-Hu Ke

Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi ,  Chung-Hu Ke

IPC: H01L31/109

CPC classification number: H01L27/095 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/7841 ,  H01L29/812

Abstract: A tunneling injection based Schottky source/drain memory cell comprising: a first semiconductor layer with a first conductivity type overlying an insulating layer, wherein the first semiconductor acts as a body region; a gate dielectric overlying the semiconductor layer; a gate electrode overlying the gate dielectric; a pair of spacers on sides of the gate electrodes; and a first Schottky barrier junction formed on a source region and a second Schottky barrier junction formed on a drain region on opposing sides of the body region. The source and the regions have an overlapping portion with the gate electrode and length of overlapping portion is preferably greater than about 5 Å. Interfacial layers are formed between the first and the second Schottky barrier regions.

Abstract translation: 一种基于隧道注入的肖特基源/漏存储单元，包括：第一半导体层，其具有覆盖绝缘层的第一导电类型，其中所述第一半导体作为体区; 覆盖半导体层的栅极电介质; 覆盖栅极电介质的栅电极; 栅电极侧面的一对间隔物; 以及形成在源区域上的第一肖特基势垒结和形成在身体区域的相对侧上的漏极区域上的第二肖特基势垒结。 源极和区域与栅电极具有重叠部分，并且重叠部分的长度优选大于约。 在第一和第二肖特基势垒区之间形成界面层。

公开(公告)号：US20060114229A1

公开(公告)日：2006-06-01

申请号：US10996459

申请日：2004-11-26

Applicant: Wen-Chin Lee ,  Hsiang-Kuang Chen

Inventor： Wen-Chin Lee ,  Hsiang-Kuang Chen

IPC: G09G5/08

CPC classification number: G06F3/0362 ,  G06F3/0383

Abstract: A magnetic oscillation metric controller applied to computer peripheral or electronic communication system essentially operating on a scrolling wheel for lateral metric control to provide precise, consistent, reliable and programmable adjustment oscillation sensitivity by driving a permanent magnet to generate signals of changed magnetic fields resulted from displacement; and retrieving the data of changed signals for achieving metric control purpose.

Abstract translation: 应用于计算机外围或电子通信系统的磁振荡度量控制器，其基本上在用于横向度量控制的滚动轮上操作，以通过驱动永久磁体以产生由位移产生的变化的磁场的信号来提供精确，一致，可靠和可编程的调节振荡灵敏度 ; 以及检索改变信号的数据以达到度量控制目的。

公开(公告)号：US07052964B2

公开(公告)日：2006-05-30

申请号：US11081919

申请日：2005-03-16

Applicant: Yee-Chia Yeo ,  Chih-Hsin Ko ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chih-Hsin Ko ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/336

CPC classification number: H01L29/7842 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

Abstract: A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.

Abstract translation: 半导体器件包括其中形成有第一和第二隔离沟槽的半导体材料区域。 第一隔离槽衬有具有低氧扩散速率的第一材料并填充绝缘材料。 第二隔离槽不是衬有第一材料，而是用绝缘材料填充。 形成在第一隔离区域附近的第一晶体管和与第二隔离区域相邻形成的第二晶体管。

公开(公告)号：US20060081875A1

公开(公告)日：2006-04-20

申请号：US10967917

申请日：2004-10-18

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L31/109 ,  H01L31/0328 ,  H01L29/76

CPC classification number: H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

Abstract translation: 晶体管结构包括覆盖衬底区域的沟道区域。 衬底区域包括具有第一晶格常数的第一半导体材料。 沟道区域包括具有第二晶格常数的第二半导体材料。 源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。 栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

公开(公告)号：US20060038199A1

公开(公告)日：2006-02-23

申请号：US10922087

申请日：2004-08-19

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L29/739

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L29/78

Abstract: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.

公开(公告)号：US06974755B2

公开(公告)日：2005-12-13

申请号：US10687377

申请日：2003-10-16

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/7833

Abstract: A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.

Abstract translation: 半导体隔离沟槽包括衬底和形成在其中的沟槽。 沟槽衬有含氮衬里并填充介电材料。 优选地，所述含氮衬垫接触位于所述沟槽附近的诸如晶体管的器件的有源区。

公开(公告)号：US20050247986A1

公开(公告)日：2005-11-10

申请号：US10840911

申请日：2004-05-06

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/7845 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S257/90

Abstract: A strained channel transistor and method for forming the the strained channel transistor including a semiconductor rate; a gate dielectric overlying a channel region; a gate rode overlying the gate dielectric; source drain extension regions and source and drain (S/D) regions; wherein a sed dielectric portion selected from the group consisting of r of stressed offset spacers disposed adjacent the gate rode and a stressed dielectric layer disposed over the gate rode including the S/D regions is disposed to exert a strain channel region.

Abstract translation: 一种应变通道晶体管和用于形成包括半导体速率的应变通道晶体管的方法; 覆盖沟道区的栅极电介质; 栅极覆盖栅极电介质; 源极漏极延伸区域和源极和漏极（S / D）区域; 其中设置选自由围绕所述栅极环配置的应力偏移间隔的r和设置在包括所述S / D区的所述栅极周围的应力介电层的施放电介质部分以施加应变通道区域。

公开(公告)号：US20050233552A1

公开(公告)日：2005-10-20

申请号：US11083537

申请日：2005-03-18

Applicant: Chung-Hu Ke ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/00 ,  H01L21/30 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/02 ,  H01L29/72 ,  H01L29/772

CPC classification number: H01L21/823807 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7848

Abstract: A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

公开(公告)号：US20050224907A1

公开(公告)日：2005-10-13

申请号：US11146661

申请日：2005-06-07

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/7833

Abstract: A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.

公开(公告)号：US20050194658A1

公开(公告)日：2005-09-08

申请号：US11114981

申请日：2005-04-26

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/78 ,  H01L31/0328 ,  H01L31/072

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.

Abstract translation: 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于衬底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。