公开(公告)号：US11056183B2

公开(公告)日：2021-07-06

申请号：US15961862

申请日：2018-04-24

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/418 ,  H01L27/11

Abstract: Various implementations described herein are directed to an integrated circuit having multiple bitcell arrays and multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays. The integrated circuit may include multiple read output ports for the multiple bitcell arrays. The single write input port is used for writing data to the multiple bitcell arrays, and the multiple read input ports are used separately for reading data from the multiple bitcell arrays for output to the multiple read output ports.

公开(公告)号：US20210019463A1

公开(公告)日：2021-01-21

申请号：US17062567

申请日：2020-10-03

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Gus Yeung ,  Marlin Wayne Frederick, JR. ,  Sriram Thyagarajan

IPC: G06F30/39 ,  G06F30/30 ,  G06F30/398

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US20200286888A1

公开(公告)日：2020-09-10

申请号：US16882634

申请日：2020-05-25

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Kumaraswamy Ramanathan ,  Damayanti Datta

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  G11C11/40 ,  H03K3/012

Abstract: Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.

公开(公告)号：US20200219890A1

公开(公告)日：2020-07-09

申请号：US16244047

申请日：2019-01-09

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Munish Kumar

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/418 ,  H01L23/528 ,  G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.

公开(公告)号：US10403643B2

公开(公告)日：2019-09-03

申请号：US15587087

申请日：2017-05-04

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Vincent Philippe Schuppe

IPC: H01L27/118 ,  H01L27/02 ,  G06F17/50

Abstract: Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first access port of the integrated circuit and a second access wire coupled to a second access port of the integrated circuit. The integrated circuit may include inverter circuitry having a first plurality of inverters coupled to the first access wire and a second plurality of inverters coupled to the second access wire. The first plurality of inverters may be positioned adjacent to the second plurality of inverters in an alternating manner.

公开(公告)号：US10177760B1

公开(公告)日：2019-01-08

申请号：US15636428

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Yicong Li ,  Hsin-Yu Chen ,  Sriram Thyagarajan

IPC: G11C5/06 ,  H03K17/687 ,  G11C5/14 ,  H01L23/64 ,  G11C7/10 ,  G06F17/50 ,  G11C8/08

Abstract: A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.

公开(公告)号：US20180323215A1

公开(公告)日：2018-11-08

申请号：US15587087

申请日：2017-05-04

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Vincent Philippe Schuppe

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  G06F17/5068 ,  H01L27/0207 ,  H01L2027/11866 ,  H01L2027/11881

Abstract: Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first access port of the integrated circuit and a second access wire coupled to a second access port of the integrated circuit. The integrated circuit may include inverter circuitry having a first plurality of inverters coupled to the first access wire and a second plurality of inverters coupled to the second access wire. The first plurality of inverters may be positioned adjacent to the second plurality of inverters in an alternating manner.

公开(公告)号：US20180225402A9

公开(公告)日：2018-08-09

申请号：US14528314

申请日：2014-10-30

Applicant: ARM Limited

Inventor： Paul DE DOOD ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Douglas Ngai Lee ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Yanbin Jiang ,  Emmanuel Jean Marie Olivier Pacaud ,  Matthieu Domonique Henri Pauly ,  Sylvia Xiuhui Li ,  Thanusree Achuthan ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US10020031B2

公开(公告)日：2018-07-10

申请号：US15401588

申请日：2017-01-09

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Gus Yeung ,  James Dennis Dodrill

IPC: G11C8/18 ,  G11C7/10 ,  G11C29/50 ,  G11C5/14 ,  G11C8/06 ,  G11C29/02 ,  G11C29/00

CPC classification number: G11C7/1012 ,  G11C5/141 ,  G11C8/06 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/702

Abstract: Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

公开(公告)号：US20180173822A1

公开(公告)日：2018-06-21

申请号：US15387373

申请日：2016-12-21

Applicant: ARM Limited

Inventor： Hongwei Zhu ,  Mouli Rajaram Chollangi ,  Hemant Joshi ,  Yew Keong Chong ,  Satinderjit Singh ,  Betsie Jacob ,  Neeraj Dogra ,  Sriram Thyagarajan

IPC: G06F17/50 ,  G06F17/30

CPC classification number: G06F17/5009 ,  G06F17/30289 ,  G06F17/5068 ,  G06F2217/12

Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data. The computing device may include a memory compiler that accesses the destination corner database and generates memory instance structures and their electronic digital automation (EDA) views for the destination corner based on the destination corner database.