公开(公告)号：US20050070082A1

公开(公告)日：2005-03-31

申请号：US10859552

申请日：2004-06-02

申请人： Thorsten Kammler ,  Karsten Wieczorek ,  Austin Frenkel

发明人： Thorsten Kammler ,  Karsten Wieczorek ,  Austin Frenkel

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： By forming a buried nickel silicide layer followed by a cobalt silicide layer in silicon-containing regions, such as a gate electrode of a field effect transistor, the superior characteristics of both silicides may be combined so as to provide the potential for further device scaling without unduly compromising the sheet resistance and the contact resistance of scaled silicon circuit features.

摘要翻译： 通过在含硅区域（例如场效应晶体管的栅电极）中形成掩埋的硅化镍层和硅化钴层之后，可以组合两种硅化物的优异特性，从而为进一步的器件成形提供潜力，而无需 不适当地损害了尺寸硅电路特征的薄层电阻和接触电阻。

公开(公告)号：US20050048731A1

公开(公告)日：2005-03-03

申请号：US10654123

申请日：2003-09-02

申请人： Jeffrey Patton ,  Mehrdad Mahanpour ,  Thorsten Kammler ,  David Brown ,  Paul Besser ,  Simon Chan ,  Austin Frenkel

发明人： Jeffrey Patton ,  Mehrdad Mahanpour ,  Thorsten Kammler ,  David Brown ,  Paul Besser ,  Simon Chan ,  Austin Frenkel

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method of forming an integrated circuit and a structure therefore is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. Shallow source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate. Deep source/drain junctions are formed in the semiconductor substrate using the sidewall spacer. A siliciding spacer is formed over the sidewall spacer after forming the shallow and deep source/drain junctions. A silicide is formed on the deep source/drain junctions adjacent the siliciding spacer, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the silicide.

摘要翻译： 因此，提供了形成集成电路和结构的方法。 在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。 在半导体衬底中形成浅源极/漏极结。 在栅极周围形成侧壁间隔物。 使用侧壁间隔物在半导体衬底中形成深源极/漏极结。 在形成浅的和深的源极/漏极结之后，在侧壁间隔物上形成硅化间隔物。 在邻近硅化间隔物的深源极/漏极结上形成硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与硅化物的接触。

公开(公告)号：US20050026380A1

公开(公告)日：2005-02-03

申请号：US10786401

申请日：2004-02-25

申请人： Thorsten Kammler ,  Katja Huy ,  Christoph Schwan

发明人： Thorsten Kammler ,  Katja Huy ,  Christoph Schwan

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： In a double-spacer or multi-spacer approach to the formation of sophisticated field effect transistors, an upper sidewall portion of a gate electrode may be effectively exposed during recessing of an outer spacer element, since the outer spacer is substantially comprised of the same material as the liner material. Consequently, the anisotropic etch process for recessing the outer sidewall spacer also efficiently removes liner residues on the upper sidewall portion and provides an increased diffusion path for a refractory metal. Additionally, the lateral extension of the silicide regions on the drain and source area may be increased by correspondingly controlling an isotropic etch process for removing oxide residues.

摘要翻译： 在形成复杂的场效应晶体管的双间隔或多间隔方法中，栅极电极的上侧壁部分可以在外间隔元件的凹陷期间被有效地暴露，因为外间隔件基本上由相同的材料组成 作为衬垫材料。 因此，用于凹陷外侧壁间隔件的各向异性蚀刻工艺还有效地去除了上侧壁部分上的衬垫残留物，并为难熔金属提供了增加的扩散路径。 此外，可以通过相应地控制用于去除氧化物残余物的各向同性蚀刻工艺来增加漏极和源极区域上的硅化物区域的横向延伸。

公开(公告)号：US06806126B1

公开(公告)日：2004-10-19

申请号：US10236200

申请日：2002-09-06

申请人： Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

发明人： Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

IPC分类号： H01L21338

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  Y10S257/90

摘要： An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

摘要翻译： 一种具有降低的栅极电阻的绝缘栅极半导体器件（100）和用于制造半导体器件（100）的方法。 栅极结构（112）形成在半导体衬底（102）的主表面（104）上。 在栅极结构（112）的侧壁附近形成连续的氮化物间隔物（118,128）。 使用单个蚀刻来蚀刻和凹入氮化物间隔物（118,128）以暴露栅极结构（112）的上部（115A，117A）。 源极（132）和漏极（134）区域形成在半导体衬底（102）中。 在栅极结构（112）和源极区（132）和漏极区（134）的顶表面（109）和暴露的上部（115A，117A）上形成硅化物区域（140,142,144）。 电极（150,152,154）形成为与相应的栅极结构（112），源极区（132）和漏极区（134）的硅化物（140,142,144）接触。

公开(公告)号：US06746927B2

公开(公告)日：2004-06-08

申请号：US10422492

申请日：2003-04-24

申请人： Thorsten Kammler ,  Karsten Wieczorek ,  Christof Streck

发明人： Thorsten Kammler ,  Karsten Wieczorek ,  Christof Streck

IPC分类号： H01L21336

CPC分类号： H01L21/28052 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： A method is provided for forming polysilicon line structures, such as gate electrodes of field effect transistors, according to which oxide spacers are removed from the sidewalls of the poly gate lines before depositing the liner oxide. Accordingly, after formation of the final spacers, the polysilicon line sidewalls are no longer covered with spacer oxide but all silicide pre-cleans can clear the poly sidewalls completely which thus leads to improved silicidation conditions, resulting in gate lines exhibiting very low sheet resistivity.

公开(公告)号：US08779529B2

公开(公告)日：2014-07-15

申请号：US13692369

申请日：2012-12-03

申请人： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

发明人： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC分类号： H01L21/02

CPC分类号： H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

摘要： A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

摘要翻译： 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US08481404B2

公开(公告)日：2013-07-09

申请号：US12838810

申请日：2010-07-19

申请人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L21/76

CPC分类号： H01L21/823871 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104

摘要： In a static memory cell, the failure rate upon forming contact elements connecting an active region with a gate electrode structure formed above an isolation region may be significantly reduced by incorporating an implantation species at a tip portion of the active region through a sidewall of the isolation trench prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region.

摘要翻译： 在静态存储单元中，通过在有源区的尖端部分通过隔离侧壁并入注入物质，可以显着地减少形成连接有源区与形成在隔离区上方的栅电极结构的接触元件之间的故障率 在用绝缘材料填充之前，该沟槽。 注入物质可以表示P型掺杂物种类和/或惰性物质，用于显着改变活性区的末端部分的材料特性。

公开(公告)号：US20120018816A1

公开(公告)日：2012-01-26

申请号：US12843350

申请日：2010-07-26

申请人： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

发明人： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

摘要： A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

摘要翻译： 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US20090032888A1

公开(公告)日：2009-02-05

申请号：US12251959

申请日：2008-10-15

申请人： William G. En ,  Thorsten Kammler ,  Eric N. Paton ,  Paul R. Besser ,  Simon Siu-Sing Chan

发明人： William G. En ,  Thorsten Kammler ,  Eric N. Paton ,  Paul R. Besser ,  Simon Siu-Sing Chan

IPC分类号： H01L29/78

CPC分类号： H01L29/7834 ,  H01L21/28035 ,  H01L21/28123 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628

摘要： A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

摘要翻译： 侧壁间隔结构邻近门结构形成，由此形成侧壁间隔结构的外表面的材料含有氮。 在其形成之后，侧壁间隔结构被退火以使后壁清洁过程的侧壁间隔结构硬化。 在清洁处理之后形成外延层。

公开(公告)号：US20080056449A1

公开(公告)日：2008-03-06

申请号：US11744313

申请日：2007-05-04

申请人： Inka Zienert ,  Jochen Rinderknecht ,  Thorsten Kammler

发明人： Inka Zienert ,  Jochen Rinderknecht ,  Thorsten Kammler

IPC分类号： G01N23/207

CPC分类号： G01N23/207 ,  G01N2223/1016 ,  G01N2223/102 ,  G01N2223/106 ,  G01N2223/611

摘要： According to an illustrative embodiment disclosed herein, a semiconductor structure comprising a first crystalline substrate and a second crystalline substrate is provided. The semiconductor structure is irradiated with a radiation. Both the first crystalline substrate and the second crystalline substrate are exposed to the radiation. At least one diffraction pattern of a crystal lattice of the first crystalline substrate and a crystal lattice of the second crystalline substrate is measured. A relative orientation of the crystal lattice of the first crystalline substrate and the crystal lattice of the second crystalline substrate is determined from the at least one diffraction pattern.

摘要翻译： 根据本文公开的说明性实施例，提供了包括第一晶体衬底和第二晶体衬底的半导体结构。 用辐射照射半导体结构。 第一晶体衬底和第二晶体衬底都暴露于辐射。 测量第一晶体衬底的晶格和第二晶体衬底的晶格的至少一个衍射图案。 从至少一个衍射图确定第一晶体衬底的晶格和第二晶体衬底的晶格的相对取向。