公开(公告)号：US06207553B1

公开(公告)日：2001-03-27

申请号：US09237258

申请日：1999-01-26

Applicant: Matthew S. Buynoski ,  Ming-Ren Lin

Inventor： Matthew S. Buynoski ,  Ming-Ren Lin

IPC: H01L214763

CPC classification number: H01L21/76885 ,  H01L21/32135

Abstract: Submicron-dimensioned metallization patterns are formed on a substrate surface by a photo-activated selective, anisotropic etching process, wherein selective portions of a metal layer are exposed to collimated UV passing through a pattern of submicron-sized openings in an overlying exposure mask. At least one photo-activatable etching material contained in a gas flowed through the space between the substrate surface and the mask selectively and anisotropically etches the exposed portions of the metal layer in thereby avoiding numerous masking and etching steps as in conventional photolithographic methodology. The inventive method is of particular utility in performing multi-level, in-laid, “back-end” metallization processing of high-density integrated circuit semiconductor devices.

Abstract translation: 通过光激活的选择性各向异性蚀刻工艺在衬底表面上形成亚微米尺寸的金属化图案，其中金属层的选择部分暴露于准直的UV穿过覆盖的曝光掩模中的亚微米尺寸的开口图案。 包含在通过衬底表面和掩模之间的空间中流动的气体中的至少一种可光致活化的蚀刻材料选择性地并且各向异性地蚀刻金属层的暴露部分，从而避免了如常规光刻方法中的许多掩模和蚀刻步骤。 本发明的方法在执行高密度集成电路半导体器件的多层次的，内置的“后端”金属化处理中是特别有用的。

公开(公告)号：US06180487B2

公开(公告)日：2001-01-30

申请号：US09427134

申请日：1999-10-25

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21762

CPC classification number: H01L21/76243

Abstract: In one embodiment, the present invention relates to a method of forming a Silicon-on-Insulator substrate involving the steps of providing a monocrystalline silicon substrate; patterning a mask over the monocrystalline silicon substrate thereby exposing a portion of the monocrystalline silicon substrate; implanting a first dosage of oxygen atoms in the exposed portion of the monocrystalline silicon substrate; removing the mask from the monocrystalline silicon substrate; implanting a second dosage of oxygen atoms without using an implantation mask in the monocrystalline silicon substrate; and annealing the oxygen implanted monocrystalline silicon substrate to provide the Silicon-on-Insulator substrate. In another embodiment, the present invention relates to a Silicon-on-Insulator structure containing a monocrystalline silicon layer; a buried oxide layer over the monocrystalline silicon layer, the buried oxide layer including a first region having a first thickness and a second region having a second thickness, wherein the first thickness is from about 30% to about 70% smaller than the second thickness; a silicon device layer over the buried oxide layer; and a heat generating device on the silicon device layer and positioned over the first region of the buried oxide layer.

Abstract translation: 在一个实施方案中，本发明涉及一种形成绝缘体上硅衬底的方法，其包括提供单晶硅衬底的步骤; 在单晶硅衬底上形成掩模，从而暴露出单晶硅衬底的一部分; 在单晶硅衬底的暴露部分中注入第一剂量的氧原子; 从单晶硅衬底去除掩模; 在单晶硅衬底中不使用注入掩模来注入第二剂量的氧原子; 以及退火氧注入的单晶硅衬底以提供绝缘体上硅绝缘体衬底。 在另一个实施方案中，本发明涉及一种含有单晶硅层的绝缘体上硅结构， 在单晶硅层上的掩埋氧化层，所述掩埋氧化物层包括具有第一厚度的第一区域和具有第二厚度的第二区域，其中所述第一厚度比所述第二厚度小约30％至约70％; 掩埋氧化物层上的硅器件层; 以及在所述硅器件层上并位于所述掩埋氧化物层的所述第一区域上方的发热器件。

公开(公告)号：US06180469B2

公开(公告)日：2001-01-30

申请号：US09187522

申请日：1998-11-06

Applicant: Shekhar Pramanick ,  Qi Xiang ,  Ming-Ren Lin

Inventor： Shekhar Pramanick ,  Qi Xiang ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/3215 ,  H01L29/66515

Abstract: Low resistivity contacts are formed on source/drain regions and gate electrodes at a suitable thickness to reduce parasitic series resistances, thereby significantly reducing consumption of underlying silicon, while significantly reducing junction leakage. Embodiments include selectively depositing a metal layer, such as nickel, on the source/drain regions and on the gate electrode and ion implanting to form a barrier layer within the nickel layers which does not react with silicon or nickel silicide during subsequent solicitation. The barrier layer confines salicidation to the relatively thin underlayer layer of nickel, thereby minimizing consumption of underlying silicon while the unsilicidized overlying nickel on the barrier layer ensures low sheet resistivity.

Abstract translation: 在源极/漏极区域和栅电极上以合适的厚度形成低电阻率接触以减少寄生串联电阻，从而显着降低底层硅的消耗，同时显着减少结漏电。 实施例包括在源极/漏极区域和栅极上选择性地沉积诸如镍的金属层和离子注入，以在镍层内形成阻挡层，其在随后的引诱期间不与硅或硅化镍反应。 阻挡层限制了相对薄的镍底层的盐析，从而最小化下层硅的消耗，而阻挡层上的无硅覆盖的镍确保了低的电阻率。

公开(公告)号：US6087231A

公开(公告)日：2000-07-11

申请号：US368854

申请日：1999-08-05

Applicant: Qi Xiang ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Ming-Ren Lin

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process using a relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening. A reaction barrier layer is deposited between the gate dielectric with the high dielectric constant and the amorphous gate electrode material to prevent a reaction between the gate dielectric and the gate electrode material. Dual gates for both an N-channel field effect transistor and a P-channel field effect transistor are formed by doping the amorphous gate electrode material with an N-type dopant for an N-channel field effect transistor, and by doping the amorphous gate electrode material with a P-type dopant for a P-channel field effect transistor. The amorphous gate electrode material in the gate opening is then annealed at a relatively low temperature, such as 600.degree. Celsius, using a solid phase crystallization process to convert the amorphous gate electrode material, such as amorphous silicon, into polycrystalline gate electrode material, such as polycrystalline silicon.

Abstract translation: 一种用于制造具有双栅极和具有高介电常数的栅极电介质的短沟道场效应晶体管的方法。 场效应晶体管最初被制造成具有牺牲栅极电介质和虚拟栅电极。 使用具有相对较高温度的任何制造工艺是用具有牺牲栅极电介质和虚拟栅电极的场效应晶体管来执行的。 从场效应晶体管蚀刻伪栅电极和牺牲栅电介质以形成栅极开口。 在栅极的侧壁和底壁上沉积具有高介电常数的电介质层，并沉积诸如非晶硅的非晶栅电极材料以填充栅极开口。 反应阻挡层沉积在具有高介电常数的栅极电介质和非晶栅电极材料之间，以防止栅极电介质和栅电极材料之间的反应。 通过用N型掺杂剂掺杂非晶栅电极材料来形成用于N沟道场效应晶体管和P沟道场效应晶体管的双栅极，并且通过掺杂非晶栅电极 具有用于P沟道场效应晶体管的P型掺杂剂的材料。 然后，使用固相结晶工艺，在诸如600℃的较低温度下将栅极开口中的非晶栅电极材料退火，将非晶态的非晶硅等非晶态栅电极材料转换为多晶栅电极材料， 作为多晶硅。

公开(公告)号：US5972773A

公开(公告)日：1999-10-26

申请号：US869466

申请日：1997-06-05

Applicant: Yowjuang W. Liu ,  Ming-Ren Lin

Inventor： Yowjuang W. Liu ,  Ming-Ren Lin

IPC: H01L21/32 ,  H01L21/762

CPC classification number: H01L21/76205 ,  H01L21/32

Abstract: A novel semiconductor fabrication process having the advantages of conventional LOCOS (process simplicity and reduced defects) while providing a scaleable, planar isolation region between active regions formed in a semiconductor substrate. The preferred process includes formation of a barrier layer and a masking layer over the substrate. An active region mask defines an exposure region of the masking layer. The exposure region is etched to form an opening, exposing a portion of barrier layer in the opening. A spacer is added inside the opening, around a perimeter of the opening to define a second exposure region. The barrier layer, and substrate, under the second exposure region, but not under the spacer, are etched to form an isolation region opening. The isolation region opening may have a suitable isolating material, such as silicon oxide, grown, filled, or some combination of both, in the isolation region opening. The spacer width and the depth of the isolation region opening are independently controllable.

Abstract translation: 一种新颖的半导体制造方法，其具有常规LOCOS（工艺简单性和降低的缺陷）的优点，同时在半导体衬底中形成的有源区域之间提供可扩展的平面隔离区域。 优选的方法包括在衬底上形成阻挡层和掩模层。 有源区掩模限定掩模层的曝光区域。 蚀刻曝光区域以形成开口，暴露开口中的阻挡层的一部分。 在开口内部，围绕开口的周边添加间隔物，以限定第二曝光区域。 在第二曝光区域下方但不在间隔物下方的阻挡层和衬底被蚀刻以形成隔离区域开口。 在隔离区开口中，隔离区开口可以具有合适的隔离材料，例如氧化硅，生长，填充或两者的某种组合。 间隔物宽度和隔离区域开口的深度是独立可控的。

公开(公告)号：US5937315A

公开(公告)日：1999-08-10

申请号：US966288

申请日：1997-11-07

Applicant: Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/665

Abstract: A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

Abstract translation: 提供了具有自对准硅化物栅极结构的深亚微米MOS器件及其形成方法，以克服多Si耗尽和硼渗透的问题。 在栅极氧化物和多晶硅栅电极之间形成第一镍硅化物层。 此外，第二镍硅化物层形成在高掺杂源/漏区上。 以这种方式，MOS器件的可靠性将得到提高。

公开(公告)号：US5893748A

公开(公告)日：1999-04-13

申请号：US799053

申请日：1997-02-10

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/0337 ,  H01L21/76816 ,  Y10S438/942 ,  Y10S438/974

Abstract: A method for producing a small feature in a semiconductor device includes depositing a mask material on an unpatterned layer in which an ultra-narrow opening is to be formed, and then masking and etching the mask material to form a narrow opening. A spacer material is then deposited on the mask material, with spacer material settling into and covering the narrow opening. Thereafter, a portion of the spacer material is removed by etching, leaving some spacer material in the opening but exposing an ultra-narrow region of the first layer at the bottom of the opening in the mask material. The ultra-narrow region left uncovered by the spacer material is smaller than the narrow region in the mask material. Once the ultra-narrow region is uncovered, material in the first layer is removed through the ultra-narrow region, by anisotropic etching, for example, to form an ultra-narrow opening in the first layer.

Abstract translation: 一种用于制造半导体器件中的小特征的方法包括：将掩模材料沉积在要形成超窄开口的未图案化层上，然后掩蔽和蚀刻掩模材料以形成窄开口。 然后将间隔物材料沉积在掩模材料上，其中间隔物材料沉降并覆盖窄开口。 此后，通过蚀刻去除间隔物材料的一部分，在开口中留下一些间隔物材料，但在掩模材料的开口底部露出第一层的超窄区域。 由间隔物材料未覆盖的超窄区域比掩模材料中的窄区域小。 一旦超窄区域被覆盖，例如通过各向异性蚀刻在第一层中的材料通过超窄区域去除，以在第一层中形成超窄的开口。

公开(公告)号：US5866473A

公开(公告)日：1999-02-02

申请号：US961853

申请日：1997-10-31

Applicant: Qi Xiang ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Ming-Ren Lin

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66575 ,  H01L21/26506 ,  H01L21/28123 ,  H01L29/42376

Abstract: A method of manufacturing an MOS transistor having a gate length dimension less than the dimension available by methods available with conventional manufacturing methods that are limited by optical diffraction in photolithography. The method includes forming a polysilicon gate structure on a gate oxide layer, forming a nitrogen-doped layer on the polysilicon gate structure, forming selected depth oxide sidewalls on the polysilicon gate structure and etching the nitrogen-doped layer and the oxide sidewalls.

Abstract translation: 一种制造栅极长度尺寸小于通过在光刻中受光学衍射限制的常规制造方法可获得的尺寸的尺寸的MOS晶体管的方法。 该方法包括在栅极氧化物层上形成多晶硅栅极结构，在多晶硅栅极结构上形成氮掺杂层，在多晶硅栅极结构上形成选定的深度氧化物侧壁，并蚀刻氮掺杂层和氧化物侧壁。

公开(公告)号：US5770519A

公开(公告)日：1998-06-23

申请号：US464305

申请日：1995-06-05

Applicant: Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76831 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract translation: 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属储存器。 储存器由铜的共形层或沉积在通孔上的金形成，以形成位于通孔中的铜或金塞。 在储存器和绝缘层之间设置阻挡层，以防止储存器扩散到绝缘层中。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积阻挡层和储层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和储存器。

公开(公告)号：US5753967A

公开(公告)日：1998-05-19

申请号：US800148

申请日：1997-02-13

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76831 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

Abstract: Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening.