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125 条记录 (耗时 0.027 秒)

    Enhanced flotation balloon
    72.
    发明申请
    Enhanced flotation balloon 审中-公开
    增强浮选气球

    公开(公告)号：US20080026667A1

    公开(公告)日：2008-01-31

    申请号：US11888051

    申请日：2007-07-31

    申请人： Brent Anderson

    发明人： Brent Anderson

    IPC分类号： A63H27/10

    CPC分类号： A63H27/10 ,  A63H2027/1025

    摘要： The present invention provides a balloon fabricated from a metalized polymeric film having to allow the balloon when filled with helium to float for a period in excess of fifteen days.

    摘要翻译： 本发明提供了一种由金属化的聚合物薄膜制成的气球，其必须允许气球充满氦气漂浮超过十五天的时间。

    Multiautoclave with Set of Vessels for Combinatorial Synthesis of Zeolites and Other Materials
    73.
    发明申请
    Multiautoclave with Set of Vessels for Combinatorial Synthesis of Zeolites and Other Materials 审中-公开
    多组分与组合组合沸石和其他材料的容器

    公开(公告)号：US20080020943A1

    公开(公告)日：2008-01-24

    申请号：US11831112

    申请日：2007-07-31

    申请人： Brent Anderson ,  Ralph Gillespie ,  Maureen Bricker

    发明人： Brent Anderson ,  Ralph Gillespie ,  Maureen Bricker

    IPC分类号： C40B50/04

    CPC分类号： B01J19/0046 ,  B01J2219/00283 ,  B01J2219/00333 ,  B01J2219/00477 ,  B01J2219/00484 ,  B01J2219/00495 ,  B01J2219/00585 ,  B01J2219/00596 ,  B01J2219/00599 ,  B01J2219/00601 ,  B01J2219/00747 ,  B01J2219/00754 ,  Y10T436/11 ,  Y10T436/113332 ,  Y10T436/114165 ,  Y10T436/25

    摘要： A vessel arrangement having a base and multiple vessels suited for simultaneously conducting a plurality of isolated experimental reactions or treatments at atmospheric process conditions or elevated temperatures and pressure condition has been developed. A component of a first material is introduced into one independent vessel through an opening in its top of the first vessel and another component of a second material is introduced into a different independent vessel through its top. Both vessels are removably located about a base at different first locations. Transformation of the components in the vessels then occurs to produce different materials therein. After completion of the experiments a displacement medium simultaneously urges the vessels from their respective locations about the base for discard or reuse after any necessary cleaning. Typically at least one property of the materials from the vessels is determined either within the vessel or after recovery of the materials.

    摘要翻译： 已经开发了具有底座和多个容器的容器装置，其适用于在大气工艺条件或升高的温度和压力条件下同时进行多个分离的实验反应或处理。 第一材料的组分通过其第一容器的顶部中的开口引入一个独立的容器中，并且第二材料的另一组分通过其顶部被引入到不同的独立容器中。 两个容器可移除地位于不同第一位置的基部周围。 然后发生容器中的组分的转化，以在其中产生不同的材料。 在完成实验之后，置换介质同时将各容器从其各自的位置推向基座，以便在任何必要的清洁之后丢弃或重新使用。 通常来自容器的材料的至少一种性质是在容器内或在材料回收之后确定的。

    MULTIPLE-GATE DEVICE WITH FLOATING BACK GATE
    74.
    发明申请
    MULTIPLE-GATE DEVICE WITH FLOATING BACK GATE 有权
    具有浮动后盖的多门装置

    公开(公告)号：US20070212834A1

    公开(公告)日：2007-09-13

    申请号：US11748576

    申请日：2007-05-15

    申请人： Brent Anderson ,  Edward Nowak

    发明人： Brent Anderson ,  Edward Nowak

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42328 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7881

    摘要： Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first insulator is thicker than the gate oxide. The floating gate is electrically insulated from other structures. Also, a second insulator is positioned between a programming gate and the floating gate. Voltage in the logic gate causes the transistor to switch on and off, while stored charge in the floating gate adjusts the threshold voltage of the transistor. The transistor can comprise a fin-type field effect transistor (FinFET), where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.

    摘要翻译： 公开了一种多栅极晶体管，其在沟道区的端部包括沟道区和源极和漏极区。 栅极氧化物位于逻辑栅极和沟道区之间，并且在浮置栅极和沟道区域之间形成第一绝缘体。 第一绝缘体比栅极氧化物厚。 浮动栅极与其他结构电绝缘。 此外，第二绝缘体位于编程门和浮动栅极之间。 逻辑门中的电压导致晶体管导通和截止，而浮置栅极中的存储电荷调节晶体管的阈值电压。 晶体管可以包括鳍式场效应晶体管（FinFET），其中沟道区域包括鳍结构的中间部分，并且源区和漏区包括鳍结构的端部。

    CMOS STRUCTURE AND METHOD INCLUDING MULTIPLE CRYSTALLOGRAPHIC PLANES
    75.
    发明申请
    CMOS STRUCTURE AND METHOD INCLUDING MULTIPLE CRYSTALLOGRAPHIC PLANES 有权
    CMOS结构和方法，包括多个水晶平面图

    公开(公告)号：US20070194373A1

    公开(公告)日：2007-08-23

    申请号：US11276274

    申请日：2006-02-22

    申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

    发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211

    摘要： A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation.

    摘要翻译： 互补金属氧化物半导体（CMOS）结构包括具有第一台面的半导体衬底，其具有沟道有效水平表面积与沟道有效垂直表面面积的第一比率。 CMOS结构还包括具有大于第一比率的相同表面积的第二比率的第二台面。 具有第一极性的第一器件使用第一台面作为通道，并且受益于增强的垂直结晶取向。 具有与第一极性不同的第二极性的第二装置使用第二台面作为通道，并且受益于增强的水平晶体取向。

    SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES
    76.
    发明申请
    SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES 有权
    具有膨胀的顶部顶部的半导体晶体管

    公开(公告)号：US20070158763A1

    公开(公告)日：2007-07-12

    申请号：US11275514

    申请日：2006-01-11

    申请人： Brent Anderson ,  Victor Chan ,  Edward Nowak

    发明人： Brent Anderson ,  Victor Chan ,  Edward Nowak

    IPC分类号： H01L29/76 ,  H01L21/3205

    CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

    摘要： A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.

    摘要翻译： 具有扩大的栅极顶部的半导体晶体管及其形成方法。 具有扩大的栅极顶部的半导体晶体管包括：（a）包括沟道区和第一和第二源极/漏极区的半导体区; 沟道区域设置在第一和第二源极/漏极区域之间，（b）与沟道区域直接物理接触的栅极电介质区域，以及（c）包括顶部和底部的栅电极区域。 底部部分与栅介质区域直接物理接触。 顶部的第一宽度大于底部的第二宽度。 栅电极区域通过栅极电介质区域与沟道区域电绝缘。

    HIGH MOBILITY PLANE FINFETS WITH EQUAL DRIVE STRENGTH
    77.
    发明申请
    HIGH MOBILITY PLANE FINFETS WITH EQUAL DRIVE STRENGTH 失效
    具有均匀驱动强度的高移动平面结构

    公开(公告)号：US20070111410A1

    公开(公告)日：2007-05-17

    申请号：US11622169

    申请日：2007-01-11

    申请人： Brent Anderson ,  Edward Nowak

    发明人： Brent Anderson ,  Edward Nowak

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

    摘要： An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and the second-type FinFET are planar with each other. A first region of the BOX layer below the first FinFET fin is thicker above the substrate when compared to a second region of the BOX layer below the second FinFET fin. Also, the second FinFET fin is taller than the first FinFET fin. The height difference between the first fin and the second fin permits the first-type FinFET to have the same drive strength as the second-type FinFET.

    摘要翻译： 集成电路结构在衬底上方具有掩埋氧化物（BOX）层，以及在BOX层上方的第一型鳍型场效应晶体管（FinFET）和第二类型FinFET。 BOX层的第二区域包括到基板的种子开口。 第一型FinFET和第二型FinFET的顶部彼此平坦。 当与第二FinFET鳍片下面的BOX层的第二区域相比时，第一FinFET鳍片下面的BOX层的第一区域比衬底上方更厚。 此外，第二个FinFET鳍片比第一个FinFET鳍片高。 第一鳍片和第二鳍片之间的高度差允许第一类型的FinFET具有与第二类型FinFET相同的驱动强度。

    SYSTEMS AND METHODS FOR MODIFYING FEATURES IN A SEMI-CONDUCTOR DEVICE
    79.
    发明申请
    SYSTEMS AND METHODS FOR MODIFYING FEATURES IN A SEMI-CONDUCTOR DEVICE 失效
    用于修改半导体器件特征的系统和方法

    公开(公告)号：US20070037098A1

    公开(公告)日：2007-02-15

    申请号：US11161624

    申请日：2005-08-10

    申请人： Brent Anderson ,  Jed Rankin

    发明人： Brent Anderson ,  Jed Rankin

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70466 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70433

    摘要： Systems and methods for modifying features of a semiconductor device. The systems and methods of the invention modify features of a semiconductor device according to the amount of exposure dose of light to which a common reticle field of a semiconductor device is exposed. A mask, or a thin film provided on a mask, having sub-resolutions provided thereon determines the amount of exposure dose to which various parts of the reticle field is exposed during the exposure. As a result, different features within the same reticle field can exhibit different dimensions even though exposed to the same exposure dose.

    摘要翻译： 用于修改半导体器件特征的系统和方法。 本发明的系统和方法根据半导体器件的公共掩模版场所暴露的光的曝光量的量来修改半导体器件的特征。 提供在掩模上的掩模或薄膜具有其上提供的子分辨率，确定在曝光期间掩模版场的各个部分暴露于哪一个曝光剂量。 结果，即使暴露于相同的曝光剂量，相同掩模版领域内的不同特征也可呈现不同的尺寸。