公开(公告)号：US5915182A

公开(公告)日：1999-06-22

申请号：US953609

申请日：1997-10-17

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/665 ,  H01L21/2257

Abstract: The method of the present invention includes forming a silicon dioxide layer. A polysilicon layer is then deposited on the silicon dioxide layer. Next, a gate structure is formed by etching. A silicon oxynitride layer is formed on the substrate and covers the gate structure. Silicon nitride side-wall spacers are formed on the side walls of the gate. An amorphous silicon layer is formed on the substrate, the side-wall spacers, and top of the polysilicon gate. Then, the source and the drain are formed. A wet oxidation is subsequently carried out to convert the amorphous silicon into a doped oxide layer. An etching process is then utilized to etch the oxide layer. Therefore, oxide side-wall spacers are formed on the silicon nitride side-wall spacers. Then, a metal silicide layer is formed on top of the gate, and on the source and the drain. The silicon nitride side-wall spacers are removed to form air gaps between the gate and the side-wall spacers. Then, a low energy pocket ion implantation is performed to doped ions into the substrate via the air gaps. Next, an oxide is formed on the substrate, spacers and over the gate. Then, a rapid thermal process (RTP) is carried out for annealing.

Abstract translation: 本发明的方法包括形成二氧化硅层。 然后在二氧化硅层上沉积多晶硅层。 接下来，通过蚀刻形成栅极结构。 在基板上形成氧氮化硅层，并覆盖栅极结构。 氮化硅侧壁隔板形成在栅极的侧壁上。 在衬底，侧壁间隔物和多晶硅栅极的顶部上形成非晶硅层。 然后，形成源极和漏极。 随后进行湿氧化以将非晶硅转化为掺杂的氧化物层。 然后利用蚀刻工艺来蚀刻氧化物层。 因此，在氮化硅侧壁间隔物上形成氧化物侧壁间隔物。 然后，在栅极的顶部以及源极和漏极上形成金属硅化物层。 去除氮化硅侧壁间隔物以在栅极和侧壁间隔物之间​​形成气隙。 然后，通过空气间隙对基底中的掺杂离子进行低能量口袋离子注入。 接下来，在衬底，间隔物和栅极上形成氧化物。 然后，进行快速热处理（RTP）进行退火。

公开(公告)号：US5913118A

公开(公告)日：1999-06-15

申请号：US990117

申请日：1997-12-12

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8242

CPC classification number: H01L27/10861

Abstract: A silicon oxide, a silicon nitride layer are patterned to define trenches region. Then, a recess portion is formed in the substrate. Subsequently, a second silicon oxide, a second silicon nitride layer are formed on the recess portion. Then, a glass layer is formed on the second silicon nitride layer and refilled into the recess portion. An etching step is performed to etch the glass layer, the second silicon nitride layer and the second silicon oxide layer to the surface of the substrate. Trenches are then created in the substrate. Then, ion implantation processes are performed to dope ions into the trenches. A dielectric layer is then deposited along the surface of the trenches and on the surface of the second silicon oxide layer, the second silicon nitride layer. A polysilicon layer is deposited on the dielectric layer and refilled into the trenches. Then, an etching back is used to etch the polysilicon layer to form a field plate. Successively, a thermal process is carried out to form an oxide layer on the field plate. Next, side-wall spacers are formed on the side walls of the field plate, and the oxide layer.

Abstract translation: 图案化氧化硅，氮化硅层以限定沟槽区域。 然后，在基板上形成凹部。 随后，在凹部上形成第二氧化硅，第二氮化硅层。 然后，在第二氮化硅层上形成玻璃层，并将其填充到凹部内。 执行蚀刻步骤以将玻璃层，第二氮化硅层和第二氧化硅层蚀刻到衬底的表面。 然后在衬底中产生沟槽。 然后，进行离子注入工艺以将离子掺杂到沟槽中。 然后沿着沟槽的表面和第二氧化硅层的表面沉积介电层，即第二氮化硅层。 多晶硅层沉积在电介质层上并重新填充到沟槽中。 然后，使用蚀刻来蚀刻多晶硅层以形成场板。 接着，进行热处理以在场板上形成氧化物层。 接下来，在场板的侧壁和氧化物层上形成侧壁间隔物。

公开(公告)号：US5869374A

公开(公告)日：1999-02-09

申请号：US64262

申请日：1998-04-22

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66583 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/66537 ,  H01L29/7836 ,  H01L29/1083

Abstract: A method for fabricating a MOS transistor with an inverse T-shaped air-gap gate structure on a semiconductor substrate is disclosed. The T-shaped air-gap gate structure reduces the parasitic resistance and capacitance; hence device structure operation speed can be improved. The method comprises the following steps: firstly, a gate hollow is defined in the pad oxide/nitride layer. Next an ultra-thin nitrogen rich dielectric as a gate oxide is formed. After that, a thin .alpha.-Si is deposited, then an ion implantation is done to form a punchthrough stopping region. After forming a CVD oxide film, an anisotropic etching is followed to form oxide spacers. An undoped silicon layer then followed to refill the gate hollow region. A CMP processes or a dry etching is done to remove silicon layer until the nitride layer is exposed. Subsequently, the oxide spacers is removed to expose a dual hollow. A LDD implantation is then implanted into the substrate. Next a pad nitride/oxide layer is successive removed to expose the substrate by a dry etching method. Subsequently, a source/drain/gate implantation and a hight temperature oxidation are carried out to grow an oxide layer and seal the dual hollow so as to form a dual air gap. At the same time the extended S/D junction are formed.

Abstract translation: 公开了一种在半导体衬底上制造具有逆T形气隙栅极结构的MOS晶体管的方法。 T形气隙栅极结构减小寄生电阻和电容; 因此可以提高装置结构的运行速度。 该方法包括以下步骤：首先在衬垫氧化物/氮化物层中限定栅极空心。 接下来，形成作为栅极氧化物的超薄富氮电介质。 之后，沉积薄的α-Si，然后进行离子注入以形成穿通停止区。 在形成CVD氧化膜之后，进行各向异性蚀刻以形成氧化物间隔物。 然后随后填充未掺杂的硅层以再填充栅极中空区域。 进行CMP处理或干蚀刻以去除硅层直至暴露氮化物层。 随后，去除氧化物间隔物以露出双重空心。 然后将LDD注入植入衬底中。 接下来，通过干蚀刻方法连续去除衬垫氮化物/氧化物层以暴露衬底。 随后，进行源极/漏极/栅极注入和高温氧化以生长氧化物层并密封双中空部以形成双气隙。 同时形成扩展的S / D结。

公开(公告)号：US5837585A

公开(公告)日：1998-11-17

申请号：US685306

申请日：1996-07-23

Applicant: Shye-Lin Wu ,  Bu-Chin Chung

Inventor： Shye-Lin Wu ,  Bu-Chin Chung

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L21/8247

CPC classification number: H01L21/28176 ,  H01L29/518 ,  H01L29/66825 ,  Y10S438/91

Abstract: The present invention discloses a method of fabricating flash memory cell for use in semiconductor memories. A nitrogen implantation step is added in the process to increase the performance of the device. The nitrogen implanted tunnel oxide exhibits a much higher electron conduction efficiency than the prior art tunnel oxides in both injection polarities. The value of charge-to-breakdown voltage of the nitrogen implanted tunnel oxide is also much larger than the narrow tunnel oxide. In addition, the electron trapping rate of the nitrogen implantation tunnel oxide is very small even under a very large electron fluence stressing (100 C/cm.sup.2).

Abstract translation: 本发明公开了一种制造用于半导体存储器的闪存单元的方法。 在该过程中添加氮注入步骤以增加器件的性能。 氮注入隧道氧化物在两种注入极性中表现出比现有技术的隧道氧化物高得多的电子传导效率。 氮注入隧道氧化物的电荷对击穿电压的值也比窄隧道氧化物大得多。 此外，即使在非常大的电子注量密度（100C / cm 2）下，氮注入隧道氧化物的电子俘获速率非常小。

公开(公告)号：US5834353A

公开(公告)日：1998-11-10

申请号：US954416

申请日：1997-10-20

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/223 ,  H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/2236 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659

Abstract: The method of the present invention includes forming a silicon oxynitride layer on a substrate. Then, a dielectric layer with high permitivity is deposited by chemical vapor deposition on the silicon oxynitride layer. Subsequently, a rapid thermal process (RTP) anneal is performed in N.sub.2 O or NO ambient to reduce the dielectric leakage. A multiple conductive layer consisting of TiN/Ti/TiN is then formed on the dielectric layer. Then, the multiple conductive layer, the dielectric layer, and the silicon oxynitride layer are patterned to form gate structure. A plasma immersion is performed to form ultra shallow extended source and drain junctions. Side wall spacers are formed on the side walls of the gate structure. Next, an ion implantation is carried out to dope ions into the substrate. Next, a rapid thermal process (RTP) anneal is performed to form shallow junctions of the source and the drain.

Abstract translation: 本发明的方法包括在基板上形成氧氮化硅层。 然后，通过化学气相沉积在氮氧化硅层上沉积具有高介电常数的电介质层。 随后，在N2O或NO环境中进行快速热处理（RTP）退火以减少电介质渗漏。 然后在电介质层上形成由TiN / Ti / TiN组成的多导电层。 然后，对多导电层，电介质层和氮氧化硅层进行图案化以形成栅极结构。 进行等离子体浸入以形成超浅扩展源极和漏极结。 在门结构的侧壁上形成侧壁间隔物。 接下来，进行离子注入以将离子掺杂到衬底中。 接下来，进行快速热处理（RTP）退火以形成源极和漏极的浅结。

公开(公告)号：US5759893A

公开(公告)日：1998-06-02

申请号：US759615

申请日：1996-12-05

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90

Abstract: A method of fabricating a rugged-crown shaped capacitor on a semiconductor substrate is provided. Specifically, the method can be applied for fabricating a storage capacitor of a DRAM cell. A doped polysilicon layer is deposited on the substrate and patterned to retain the portion of the doped polysilicon layer within a planned region of the capacitor. Next, an undoped polysilicon layer is deposited on the doped polysilicon layer and the substrate and etched back as undoped polysilicon spacers. Then the doped layer and the undoped spacers are selectively etched by a hot H.sub.3 PO.sub.4 solution to form a crown-shaped node of the capacitor with a rugged surface. Then the undoped portion of the crown-shaped node of the capacitor is doped and the rugged-crown shaped node forms a conductive plate of the DRAM capacitor, providing a rugged-crown shaped capacitor having a larger area to increase its capacitance.

Abstract translation: 提供了一种在半导体衬底上制造凹凸冠状电容器的方法。 具体地说，该方法可以用于制造DRAM单元的存储电容器。 掺杂多晶硅层沉积在衬底上并被图案化以将掺杂多晶硅层的部分保持在电容器的规划区域内。 接下来，在掺杂多晶硅层和衬底上沉积未掺杂的多晶硅层，并将其作为未掺杂的多晶硅间隔物回蚀刻。 然后通过热的H3PO4溶液选择性地蚀刻掺杂层和未掺杂的间隔物，以形成具有粗糙表面的电容器的冠状节点。 然后，电容器的冠状节点的未掺杂部分被掺杂，并且粗糙的冠形节点形成DRAM电容器的导电板，提供具有较大面积的坚固冠状电容器以增加其电容。

公开(公告)号：US5750431A

公开(公告)日：1998-05-12

申请号：US881774

申请日：1997-06-24

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91 ,  Y10S148/014

Abstract: A method for fabricating a stacked capacitor is disclosed. The method includes forming successively a first dielectric layer, a first polysilicon layer and an insulation layer over a semiconductor substrate. The three layers are patterned to have a window in which a portion of the substrate is exposed. A second polysilicon layer is deposited over the insulation layer and filled in the window. The second polysilicon layer and the insulation layer are patterned to form an island. A dielectric spacer around the island is formed. Moreover, the second polysilicon layer over the insulation layer and the first polysilicon uncovered by the island are removed. The insulation layer in the island is then removed to leave a polysilicon rod surrounded by the dielectric spacer. Polysilicon spacers around the polysilicon rod and the dielectric spacer are formed and the dielectric spacer is removed, thereby forming a lower electrode. Finally, a second dielectric layer and an upper electrode are formed over the lower electrode.

Abstract translation: 公开了一种用于制造叠层电容器的方法。 该方法包括在半导体衬底上连续形成第一介电层，第一多晶硅层和绝缘层。 将三层图案化成具有其中露出基板的一部分的窗口。 第二多晶硅层沉积在绝缘层上并填充在窗口中。 图案化第二多晶硅层和绝缘层以形成岛。 形成岛周围的电介质隔片。 此外，除去绝缘层上的第二多晶硅层和未被岛覆盖的第一多晶硅。 然后去除岛中的绝缘层以留下被电介质间隔物包围的多晶硅棒。 形成多晶硅棒和电介质间隔物周围的多晶硅间隔物，去除电介质间隔物，从而形成下电极。 最后，在下电极上形成第二电介质层和上电极。

公开(公告)号：US5429966A

公开(公告)日：1995-07-04

申请号：US96505

申请日：1993-07-22

Applicant: Shye-Lin Wu ,  Chung-Len Lee ,  Tan-Fu Lei

Inventor： Shye-Lin Wu ,  Chung-Len Lee ,  Tan-Fu Lei

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/265

CPC classification number: H01L21/28211 ,  H01L29/51 ,  Y10S438/964

Abstract: Disclosed is a thin textured tunnel oxide prepared by thermal oxidation of a thin polysilicon film on Si substrate. Due to the rapid diffusion of oxygen through grain boundries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at grain boundries, a textured Si/SiO.sub.2 interface is obtained. The textured Si/SiO.sub.2 interface results in localized high fields and causes a much higher electron injection rate. EEPROM memory cells having the textured Si/SiO.sub.2 exhibit a lower electron trapping rate and a lower interface state generation rate even under high field operation.

Abstract translation: 公开了通过Si衬底上的薄多晶硅膜的热氧化制备的薄纹理隧道氧化物。 由于氧通过薄多晶硅膜的晶界快速扩散到Si衬底中，并且在晶界处提高了氧化速率，因此获得了织构化的Si / SiO 2界面。 纹理化的Si / SiO 2界面导致局部高场并导致高得多的电子注入速率。 具有织构化的Si / SiO 2的EEPROM存储单元即使在高场操作下也表现出较低的电子俘获速率和较低的界面状态产生速率。

公开(公告)号：US07491633B2

公开(公告)日：2009-02-17

申请号：US11453933

申请日：2006-06-16

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01L29/872 ,  H01L29/66143 ,  H01L29/8725

Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.

Abstract translation: 公开了一种功率肖特基整流器及其制造方法。 肖特基整流器件包括通过在沟槽的侧壁上使用氮化物间隔物作为热氧化掩模在沟槽的底部生长的LOCOS结构。 然后在第一沟槽中填充多晶硅层。 在LOCOS结构下，可选地形成p掺杂区域，以在器件经历反向偏置时使电流泄漏最小化。 通过溅射和退火步骤形成的肖特基势垒硅化物层形成在外延层和多晶硅层的上表面上。 然后在肖特基势垒硅化物层上形成用作阳极的顶部金属层，并延伸以覆盖端接沟槽的一部分场氧化物区域。 然后，在与顶部金属层相对的基板的背面上形成用作阴极电极的金属层。

公开(公告)号：US06936905B2

公开(公告)日：2005-08-30

申请号：US10421781

申请日：2003-04-24

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/329 ,  H01L29/872 ,  H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108

CPC classification number: H01L29/66143 ,  H01L29/872

Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device including a LOCOS structure and two p-type doping regions, which are positioned one above another therein to isolate cells so as to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n− drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n− drift layer; a pair of field oxide regions and termination region formed into the n− drift layer and each spaced from each other by the mesas, where the mesas have metal silicide layer formed thereon. A top metal layer formed on the field oxide regions and termination region and contact with the silicide layer. Under each of field oxide regions and termination region is a p doped and p− doped region cascade which provide depleted regions enclosed the p− doped regions to blocking the leakage current while a reverse bias voltage is exerted to the Schottky power rectifier diode.

Abstract translation: 公开了一种功率肖特基整流器及其制造方法。 肖特基整流器件包括LOCOS结构和两个p型掺杂区域，其位于另一个之上，以隔离电池，以避免击穿电压过早。 肖特基整流器件包括：形成在n +衬底上的n-漂移层; 形成在与n漂移层相对的n +衬底的表面上的阴极金属层; 一对场氧化物区域和终端区域，形成在n漂移层中，并且每一个由台面彼此隔开，其中台面在其上形成金属硅化物层。 形成在场氧化物区域和终止区域上并与硅化物层接触的顶部金属层。 在每个场氧化物区域和终止区域内是p掺杂和p-掺杂区域级联，其提供封装p掺杂区域的耗尽区域以阻挡漏电流，同时反向偏置电压施加到肖特基功率整流二极管。