公开(公告)号：US09054221B2

公开(公告)日：2015-06-09

申请号：US13510807

申请日：2011-11-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 半导体器件包括：SOI晶片，其包括半导体衬底，掩埋绝缘层和半导体层，其中所述掩埋绝缘层设置在所述半导体衬底上，并且所述半导体层设置在所述掩埋绝缘层上; 在SOI晶片中彼此相邻形成的多个MOSFET，其中每个MOSFET包括形成在半导体衬底中的相应后栅; 以及多个浅沟槽隔离，其中每一个均形成在各个相邻的MOSFET之间，以将各个相邻的MOSFET彼此隔离，其中相应的相邻MOSFET在半导体内部和相应的后栅极直接接触并与之直接接触。 衬底，并且PNP结或NPN结由公共背栅隔离区和相应的相邻MOSFET的相应背栅形成。 根据本公开，两个相邻MOSFET的相应背板通过浅沟槽隔离彼此隔离。 此外，两个相邻的MOSFET也通过由两个相邻MOSFET的相应后沿和公共背栅隔离形成的PNP或NPN结彼此隔离。 结果，该器件结构具有比现有技术的MOSFET更好的绝缘效果，并且大大降低了突破的可能性。

公开(公告)号：US08981454B2

公开(公告)日：2015-03-17

申请号：US13061461

申请日：2010-09-25

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/845 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7881

摘要： The present application discloses a non-volatile memory device, comprising a semiconductor fin on an insulating layer; a channel region at a central portion of the semiconductor fin; source/drain regions on both sides of the semiconductor fin; a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate. The non-volatile memory device reduces a short channel effect, has an increased memory density, and is cost effective.

摘要翻译： 本申请公开了一种非易失性存储器件，其包括绝缘层上的半导体鳍片; 在半导体鳍片的中心部分处的沟道区域; 半导体鳍片两侧的源极/漏极区域; 布置在半导体鳍片的第一侧并沿远离半导体鳍片的方向延伸的浮动栅极; 以及布置在所述浮动栅极的顶部上或覆盖所述浮动栅极的顶部和侧壁部分的第一控制栅极。 非易失性存储器件减少短通道效应，具有增加的存储器密度，并且是成本有效的。

公开(公告)号：US08952453B2

公开(公告)日：2015-02-10

申请号：US13580053

申请日：2011-11-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/78648

摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.

摘要翻译： 本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅极堆叠; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一伪栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及 第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。

公开(公告)号：US08928089B2

公开(公告)日：2015-01-06

申请号：US13201827

申请日：2011-02-24

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L21/70 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： A semiconductor structure and a method for forming the same are provided. The structure comprises a semiconductor substrate (100) with an nMOSFET region (102) and a pMOSFET region (104) on it. An nMOSFET structure and a pMOSFET structure are formed in the nMOSFET region (102) and the pMOSFET region (104), respectively. The nMOSFET structure comprises a first channel region (182) formed in the nMOSFET region (102) and a first gate stack formed in the first channel region (182). The nMOSFET structure is covered with a compressive-stressed material layer (130) to apply a tensile stress to the first channel region (182). The pMOSFET structure comprises a second channel region (184) formed in the pMOSFET region (104) and a second gate stack formed in the second channel region (184). The pMOSFET structure is covered with a tensile-stressed material layer (140) to apply a compressive stress to the second channel region (184).

摘要翻译： 提供半导体结构及其形成方法。 该结构包括其上具有nMOSFET区域（102）和pMOSFET区域（104）的半导体衬底（100）。 nMOSFET结构和pMOSFET结构分别形成在nMOSFET区域（102）和pMOSFET区域（104）中。 nMOSFET结构包括形成在nMOSFET区域（102）中的第一沟道区（182）和形成在第一沟道区（182）中的第一栅叠层。 nMOSFET结构用压应力材料层（130）覆盖，以向第一沟道区域（182）施加拉伸应力。 pMOSFET结构包括形成在pMOSFET区域（104）中的第二沟道区（184）和形成在第二沟道区（184）中的第二栅叠层。 pMOSFET结构被拉伸应力材料层（140）覆盖，以向第二通道区域（184）施加压缩应力。

公开(公告)号：US08895403B2

公开(公告)日：2014-11-25

申请号：US13698276

申请日：2011-11-30

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/02107 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203

摘要： A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost.

摘要翻译： 在本发明中公开了晶体管，晶体管的制造方法以及包括该晶体管的半导体器件。 制造晶体管的方法可以包括：提供衬底并在衬底上形成第一绝缘层; 限定所述第一绝缘层上的第一器件区域; 在所述第一绝缘层上形成围绕所述第一器件区域的间隔物; 在所述第一绝缘层上限定第二器件区域，其中所述第二器件区域通过所述间隔物与所述第一器件区域隔离; 以及分别在第一和第二器件区域中形成晶体管结构。 本发明的晶体管的制造方法大大降低了隔离所需的空间，显着地降低了工艺的复杂性，大大降低了制造成本。

公开(公告)号：US20140299919A1

公开(公告)日：2014-10-09

申请号：US14354648

申请日：2012-07-31

申请人： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

发明人： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer on the substrate; forming a spacer on opposite sides of the sacrificial gate stack; and forming source/drain regions with the spacer as a mask.

摘要翻译： 提供半导体器件及其制造方法。 在一个实施例中，该方法包括：在衬底上生长第一外延层; 在所述第一外延层上形成牺牲栅叠层; 选择性地蚀刻第一外延层; 在衬底上生长并原位掺杂第二外延层; 在所述牺牲栅极堆叠的相对侧上形成间隔物; 以及用间隔物形成源极/漏极区域作为掩模。

公开(公告)号：US08846488B2

公开(公告)日：2014-09-30

申请号：US13578598

申请日：2011-11-30

申请人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/265

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L29/7842 ,  H01L29/7847

摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分 引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。 根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

公开(公告)号：US08841777B2

公开(公告)日：2014-09-23

申请号：US12685954

申请日：2010-01-12

申请人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

发明人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L21/48 ,  H01L21/52 ,  H01L21/40 ,  H01L21/20 ,  H01L27/06 ,  H01L21/768

CPC分类号： H01L21/76841 ,  H01L21/2007 ,  H01L27/0688 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

摘要： Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

摘要翻译： 形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。 或者，形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。 在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。 第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。

公开(公告)号：US08829587B2

公开(公告)日：2014-09-09

申请号：US13003585

申请日：2010-09-19

申请人： Huilong Zhu

发明人： Huilong Zhu

IPC分类号： H01L29/768 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory device includes a semiconductor substrate, a gate stack formed on the semiconductor substrate; a channel region below the gate stack; spacers outside the gate stack; and source/drain regions outside the channel region and in the semiconductor substrate, in which the gate stack includes a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer and inner walls of the spacers; a second gate dielectric layer covering a surface of the first conductive layer; and a second conductive layer covering a surface of the second gate dielectric layer. A method for manufacturing a flash memory device disclosed herein.

摘要翻译： 闪存器件包括半导体衬底，形成在半导体衬底上的栅叠层; 栅堆叠下方的沟道区; 栅极叠层之外的间隔物; 以及沟道区域和半导体衬底之外的源极/漏极区域，其中栅极堆叠层包括沟道区域上的第一栅极介电层; 覆盖所述第一栅极电介质层的上表面和所述间隔物的内壁的第一导电层; 覆盖所述第一导电层的表面的第二栅极介电层; 以及覆盖所述第二栅极介电层的表面的第二导电层。 本文公开的闪存器件的制造方法。

公开(公告)号：US08815698B2

公开(公告)日：2014-08-26

申请号：US13381636

申请日：2011-07-26

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L27/04 ,  H01L21/76 ,  H01L21/8238 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66651

摘要： A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.

摘要翻译： 提供了半导体技术领域中的阱区形成方法和半导体基底。 一种方法包括：在半导体衬底中形成隔离区以隔离有源区; 选择所述有源区域中的至少一个，以及在所选择的有源区域中形成第一阱区域; 形成掩模以覆盖所选择的有源区，并蚀刻其余的有源区，以便形成沟槽; 并通过外延生长半导体材料以填充凹槽。 另一种方法包括：在半导体衬底中形成用于隔离有源区的隔离区; 在活跃区域形成井区; 蚀刻有源区以形成凹槽，使得凹槽具有小于或等于阱区深度的深度; 并通过外延生长半导体材料以填充凹槽。