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    Bonded structure employing metal semiconductor alloy bonding
    1.
    发明授权
    Bonded structure employing metal semiconductor alloy bonding 有权
    使用金属半导体合金结合的结合结构

    公开(公告)号：US08841777B2

    公开(公告)日：2014-09-23

    申请号：US12685954

    申请日：2010-01-12

    申请人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

    发明人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

    IPC分类号： H01L21/48 ,  H01L21/52 ,  H01L21/40 ,  H01L21/20 ,  H01L27/06 ,  H01L21/768

    CPC分类号： H01L21/76841 ,  H01L21/2007 ,  H01L27/0688 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

    摘要： Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

    摘要翻译： 形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。 或者，形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。 在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。 第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。

    BONDED STRUCTURE EMPLOYING METAL SEMICONDUCTOR ALLOY BONDING
    4.
    发明申请
    BONDED STRUCTURE EMPLOYING METAL SEMICONDUCTOR ALLOY BONDING 有权
    使用金属半导体合金接合的结合结构

    公开(公告)号：US20110168434A1

    公开(公告)日：2011-07-14

    申请号：US12685954

    申请日：2010-01-12

    申请人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

    发明人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

    IPC分类号： H05K1/09 ,  B05D5/12 ,  H05K1/02

    CPC分类号： H01L21/76841 ,  H01L21/2007 ,  H01L27/0688 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

    摘要： Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

    摘要翻译： 形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。 或者，形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。 在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。 第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。

    Ionizing radiation blocking in IC chip to reduce soft errors
    9.
    发明授权
    Ionizing radiation blocking in IC chip to reduce soft errors 有权
    IC芯片中的电离辐射阻断减少软错误

    公开(公告)号：US08999764B2

    公开(公告)日：2015-04-07

    申请号：US11836819

    申请日：2007-08-10

    申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

    发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

    IPC分类号： H01L21/00 ,  H01L23/532 ,  H01L23/556

    CPC分类号： H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

    摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

    摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

    Edge protection seal for bonded substrates
    10.
    发明授权
    Edge protection seal for bonded substrates 有权
    粘合基材的边缘保护密封

    公开(公告)号：US08679611B2

    公开(公告)日：2014-03-25

    申请号：US13556369

    申请日：2012-07-24

    申请人： Mukta G. Farooq ,  Emily Kinser ,  Richard S. Wise ,  Hakeem B. S. Akinmade-Yusuff

    发明人： Mukta G. Farooq ,  Emily Kinser ,  Richard S. Wise ,  Hakeem B. S. Akinmade-Yusuff

    IPC分类号： B32B3/02 ,  B29C65/48

    CPC分类号： H01L21/02263 ,  H01L21/187 ,  H01L21/76898 ,  H01L25/074 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.

    摘要翻译： 介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。 介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。 介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。 此外，介电材料层密封第一和第二基板之间的界面的整个周边。 如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。