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    Bonded structure employing metal semiconductor alloy bonding
    1.
    发明授权
    Bonded structure employing metal semiconductor alloy bonding 有权
    使用金属半导体合金结合的结合结构

    公开(公告)号：US08841777B2

    公开(公告)日：2014-09-23

    申请号：US12685954

    申请日：2010-01-12

    申请人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

    发明人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

    IPC分类号： H01L21/48 ,  H01L21/52 ,  H01L21/40 ,  H01L21/20 ,  H01L27/06 ,  H01L21/768

    CPC分类号： H01L21/76841 ,  H01L21/2007 ,  H01L27/0688 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

    摘要： Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

    摘要翻译： 形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。 或者，形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。 在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。 第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。

    BONDED STRUCTURE EMPLOYING METAL SEMICONDUCTOR ALLOY BONDING
    4.
    发明申请
    BONDED STRUCTURE EMPLOYING METAL SEMICONDUCTOR ALLOY BONDING 有权
    使用金属半导体合金接合的结合结构

    公开(公告)号：US20110168434A1

    公开(公告)日：2011-07-14

    申请号：US12685954

    申请日：2010-01-12

    申请人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

    发明人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

    IPC分类号： H05K1/09 ,  B05D5/12 ,  H05K1/02

    CPC分类号： H01L21/76841 ,  H01L21/2007 ,  H01L27/0688 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

    摘要： Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

    摘要翻译： 形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。 或者，形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。 在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。 第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。

    Enhancing MOSFET performance with corner stresses of STI
    10.
    发明授权
    Enhancing MOSFET performance with corner stresses of STI 有权
    通过STI拐角应力增强MOSFET性能

    公开(公告)号：US09356025B2

    公开(公告)日：2016-05-31

    申请号：US14348579

    申请日：2012-03-29

    申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

    发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

    IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66

    CPC分类号： H01L27/092 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66575 ,  H01L29/7846

    摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.

    摘要翻译： 本发明涉及利用STI的拐角应力来增强MOSFET的性能。 一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光​​区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准 地区。