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71.发明授权Non-evacuated lateral fed employing emitter-anode spacing less than mean free path distance of an electron in air 失效使用发射极 - 阳极间距的非抽真空横向馈电小于电子在空气中的平均自由程距离
公开(公告)号：US5736810A
公开(公告)日：1998-04-07
申请号：US641252
申请日：1996-04-30
CPC分类号： H01J3/022 , H01J2201/30423
摘要： Lateral field emission devices ("FEDs") for display elements and methods of fabrication are set forth. The FED includes a thin-film emitter oriented parallel to, and disposed above, a substrate. The FED further includes a columnar shaped anode having a first lateral surface. A phosphor layer is disposed adjacent to the first lateral surface. Specifically, the anode is oriented such that the lateral surface and adjacent phosphor layer are perpendicular to the substrate. The emitter has a tip which is spaced less than the mean free distance of an electron in air from the phosphor layer. Operationally, when a voltage potential is applied between said anode and said emitter, electrons are emitted from the tip of the emitter into the phosphor layer causing the phosphor layer to emit electromagnetic energy. Further specific details of the field emission device, fabrication method, method of operation, and associated display are set forth.
摘要翻译： 阐述了用于显示元件和制造方法的侧面场致发射器件（“FED”）。 FED包括平行于并设置在基板上方的薄膜发射极。 FED还包括具有第一侧表面的柱状阳极。 磷光体层邻近第一侧面设置。 具体地，阳极被定向成使得侧表面和相邻磷光体层垂直于衬底。 发射器具有一个尖端，该尖端的距离小于空气中的电子与荧光体层的平均自由距离。 在工作上，当在所述阳极和所述发射极之间施加电压电位时，电子从发射极的尖端发射到荧光体层中，从而使荧光层发射电磁能。 阐述了场致发射装置，制造方法，操作方法和相关显示器的进一步具体细节。
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72.发明授权
公开(公告)号：US5670388A
公开(公告)日：1997-09-23
申请号：US542592
申请日：1995-10-13
IPC分类号： H01L29/786 , H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L2924/0002 , Y10S148/15 , Y10S438/98
摘要： Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.
摘要翻译： 提出了用于形成用于SOI FET的体衬底连接器的结构和方法。 该连接器在不干扰源极和漏极的装置的一侧基本上与栅极导体共同对准。 因此，本体保持靠近基底电位，并且连接器为多数载体快速离开身体提供了路径。 通过以不扰乱由栅极成像的电荷的方式接触SOI MOSFET器件的主体，消除寄生双极效应，同时保持SOI MOSFET器件的期望属性，例如低衬底偏置灵敏度和陡峭的次阈值斜率 。 通过形成与栅极导体基本上共同对准的连接器，连接使用很少或没有表面积。
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公开(公告)号：US07911025B2
公开(公告)日：2011-03-22
申请号：US12127080
申请日：2008-05-27
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.
摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。 还提供了制造和编程保险丝/反熔丝结构的方法。
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公开(公告)号：US07863122B2
公开(公告)日：2011-01-04
申请号：US12133440
申请日：2008-06-05
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
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75.发明授权Dielectric material with reduced dielectric constant and methods of manufacturing the same 失效具有降低介电常数的介电材料及其制造方法公开(公告)号：US07732322B2
公开(公告)日：2010-06-08
申请号：US11360350
申请日：2006-02-23
IPC分类号： H01L21/4763
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02238 , H01L21/02252 , H01L21/31633 , H01L21/7682 , H01L21/76831
摘要： In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了制造介电常数降低的介电材料的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成包括沟槽的电介质材料层; 以及（2）通过沿着沟槽的侧壁和底部中的至少一个形成电介质材料层中的多个气隙，从而在电介质材料层中形成包层区域，从而降低电介质材料的有效介电常数 。 提供了许多其他方面。
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公开(公告)号：US07667248B2
公开(公告)日：2010-02-23
申请号：US12028916
申请日：2008-02-11
IPC分类号： H01L29/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
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77.发明授权Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate 失效具有减小的结电容和漏极引起的屏障降低的半导体器件结构以及用于制造这种器件结构和用于制造绝缘体上半导体衬底的方法公开(公告)号：US07659178B2
公开(公告)日：2010-02-09
申请号：US11379655
申请日：2006-04-21
IPC分类号： H01L21/311 , H01L21/3115
CPC分类号： H01L29/66545 , H01L29/51 , H01L29/513 , H01L29/66636 , H01L29/66772 , H01L29/78603 , Y10S438/96
摘要： Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.
摘要翻译： 具有减小的结电容和漏极引发的屏障降低的半导体器件结构，用于制造这种器件结构的方法以及用于形成绝缘体上半导体衬底的方法。 半导体结构包括半导体层和设置在半导体层和衬底之间的电介质层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。 在一个实施例中，第一电介质区域的介电常数可以小于约3.9，并且第二电介质区域的介电常数可以大于约十（10）。 绝缘体上半导体衬底包括通过高介电常数材料的绝缘体层与本体层分离的半导体层。 制造方法包括修改介电层的区域以具有较低的介电常数。
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公开(公告)号：US07470929B2
公开(公告)日：2008-12-30
申请号：US11491721
申请日：2006-07-24
IPC分类号： H01L29/10
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.
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79.发明申请STRUCTURE INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES FOR USE IN SRAM DEVICES 审中-公开结构在SRAM器件中使用的半导体器件结构公开(公告)号：US20080251878A1
公开(公告)日：2008-10-16
申请号：US11876030
申请日：2007-10-22
申请人： Jack Allan Mandelman , Haining Yang
发明人： Jack Allan Mandelman , Haining Yang
IPC分类号： H01L29/00
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： Device structures embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes static random access memory (SRAM) devices. The design structure includes a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The design structure further comprises an electrically connective bridge extending across the first semiconductor region. A portion of the electrically connective bridge electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure.
摘要翻译： 体现在用于设计，制造或测试其中设计结构包括静态随机存取存储器（SRAM）设备的设计的机器可读介质中的设备结构。 该设计结构包括设置在第一和第二半导体区域之间的介质区域和在第一和第二半导体区域之间延伸的栅极导体结构。 栅极导体结构具有覆盖第一半导体区域的第一侧壁。 该设计结构还包括延伸跨越第一半导体区域的电连接桥。 电连接桥的一部分将第一半导体区域中的杂质掺杂区域与栅极导体结构的第一侧壁电连接。
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公开(公告)号：US20080142891A1
公开(公告)日：2008-06-19
申请号：US12028916
申请日：2008-02-11
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
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