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公开(公告)号：US07480830B2
公开(公告)日：2009-01-20
申请号：US11937568
申请日：2007-11-09
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C5/04 , G11C29/022 , G11C2029/4002
摘要： A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.
摘要翻译： 缓冲存储器模块，包括下游缓冲器，下游接收器，上游驱动器，上游接收器。 下游缓冲器和下游接收器都适于连接到分组级联互连存储器子系统中的下游存储器总线。 上游驱动器和上游接收器都适于连接到存储器子系统中的上游存储器总线。 在对存储器模块进行测试期间，上游驱动器连接到下游接收器，下游驱动器连接到上游接收器。 存储器模块还包括一个或多个存储寄存器，微处理器和服务接口端口。 微处理器包括用于执行存储器模块的测试的指令，包括将测试结果存储在存储寄存器中。 服务接口端口接收启动测试执行的服务接口信号，并访问存储寄存器以确定测试结果。
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公开(公告)号：US07403409B2
公开(公告)日：2008-07-22
申请号：US11735640
申请日：2007-04-16
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。
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公开(公告)号：US07058131B2
公开(公告)日：2006-06-06
申请号：US10007191
申请日：2001-11-08
CPC分类号： H04L25/0298 , H04L1/242 , H04L7/0008 , H04L25/0272 , H04L25/028 , H04L25/0292
摘要： A high speed signal transmission system employs differential receivers for receiving data signals transmitted over circuit transmission lines. One input each receiver is coupled to the output of a transmission line and to a termination network. The termination network generates a termination voltage and a source impedance that is matched to the characteristic impedance of the transmission line. The other input of the receiver is coupled to a reference voltage. The termination voltage may be adjusted by programming signals while keeping the source impedance constant and matched to the transmission line. A test mode may be employed where known data signals are transmitted and received and the termination voltage is adjusted while monitoring the states of the received signals on the output of the receivers. In this manner, the system may be optimized or tested for noise margin in an actual operation environment without resorting to probing methods. The clock signal used to time the transmission of the data signals is likewise transmitted along with its complement on two additional transmission lines. The clock signals are received in termination networks like the data signals. Additionally, the two clock signals are coupled to the reference signal with resistor/capacitor filter networks generating a low frequency tracking voltage superimposed on the reference voltage further improving noise margins.
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公开(公告)号：US5825226A
公开(公告)日：1998-10-20
申请号：US529850
申请日：1995-09-18
CPC分类号： H03L7/0895 , H03K5/133 , H03L7/0812
摘要： A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of the external clock signal variable delay path. The delay equalization circuit also includes a delay path in the feedback loop, and second element for creating a second pulse in proportion to the delay of the internal delay path. Finally, the circuit contains a comparison device. The comparison device compares the first and second pulses. The comparison device outputs a difference signal in proportion to the difference in the external and internal path delays. That difference signal is fed back and used to control the external path delay such that the external delay is driven to be substantially equal to the internal delay, minimizing the static phase error of the PLL device.
摘要翻译： 提供了用于最小化PLL中的静态相位误差的延迟均衡电路。 延迟均衡电路包括外部时钟信号可变延迟路径和用于产生具有与外部时钟信号可变延迟路径的延迟成比例的宽度的脉冲的元件。 延迟均衡电路还包括反馈回路中的延迟路径，以及用于与内部延迟路径的延迟成比例地产生第二脉冲的第二元件。 最后，该电路包含比较装置。 比较装置比较第一和第二脉冲。 比较装置与外部和内部路径延迟的差异成比例地输出差分信号。 该差分信号被反馈并用于控制外部路径延迟，使得外部延迟被驱动为基本上等于内部延迟，从而最小化PLL器件的静态相位误差。
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公开(公告)号：US5627456A
公开(公告)日：1997-05-06
申请号：US477208
申请日：1995-06-07
CPC分类号： G05F3/262 , Y10S323/907
摘要： An integrated current reference circuit provides a current output with a predetermined temperature coefficient, suitably zero, to provide constant current over temperature variations. The circuit is formed of only Field Effect Transistors (FETs), allowing the circuit to be implemented using conventional CMOS fabrication techniques. A current mirror provides a reference current in both branches of the circuit. The output of the current mirror is coupled to a circuit providing an imbalance in resistance between the two branches, and an offsetting imbalance in voltages between the two branches, resulting in a reference current that has a predetermined temperature coefficient. An output current is provided which is proportional to the reference current and thus has the same temperature coefficient as the reference current.
摘要翻译： 集成电流参考电路为电流输出提供预定的温度系数，适当地为零，以提供恒定电流超过温度变化。 该电路仅由场效应晶体管（FET）形成，允许使用常规CMOS制造技术实现电路。 电流镜在电路的两个分支中提供参考电流。 电流镜的输出耦合到提供两个分支之间的电阻不平衡的电路和两个分支之间的电压的偏移不平衡，导致具有预定温度系数的参考电流。 提供与参考电流成比例的输出电流，因此具有与参考电流相同的温度系数。
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公开(公告)号：US5239289A
公开(公告)日：1993-08-24
申请号：US754856
申请日：1991-09-04
IPC分类号： H01F17/00
CPC分类号： H01F17/0006
摘要： A compact, wide range inductor capable of being trimmed to a desired frequency value, comprising at least two individually tunable inductive elements of different resolution, disposed upon an insulative support. The inductor is usually placed within a hybrid circuit and trimmed after component population.
摘要翻译： 一种紧凑的宽范围电感器，其能够被修剪到期望的频率值，包括设置在绝缘支撑上的至少两个具有不同分辨率的可单独调谐的感应元件。 电感通常放置在混合电路中，并在组件总数之后进行修整。
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公开(公告)号：US5212716A
公开(公告)日：1993-05-18
申请号：US650516
申请日：1991-02-05
CPC分类号： H04L7/0338 , H03L7/0814
摘要： Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge transitions of a serial data stream relative to a local clock signal. The local clock signal is coupled to a delay line having a plurality of serially connected delay elements, each of which outputs a delay clock of different phase. The sorting circuit includes an extraction circuit coupled to receive the serial data stream for detecting edge transitions in the serial stream and outputting a pulse of predefined duration in response to each detected transition. Coupled to the extraction circuit output is a non-sequential logic circuit, which is also coupled to the local clock through the delay line. The non-sequential logic circuit combines the outputted extraction circuit pulse and the plurality of delay clocks for sorting the pulse relative to the delay clocks. Specific embodiments for the extraction circuit and non-sequential logic circuitry are depicted and described herein.
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公开(公告)号：US5185768A
公开(公告)日：1993-02-09
申请号：US594242
申请日：1990-10-09
CPC分类号： H04L7/0338
摘要： A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the integration and periodic analysis of a plurality of sorted data edge transitions of a received serial data stream. A retiming clock phase is selected from a plurality of locally generated clock signals of different phase. The retiming clock selection is preferably reevaluated after N data edge transition sorts. The resultant data edge histogram can be cumulative of all sorted transitions or merely cumulative of the last N sorted transitions. Corresponding methods and apparatus are described.
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