公开(公告)号：US20150372088A1

公开(公告)日：2015-12-24

申请号：US14313785

申请日：2014-06-24

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/10 ,  H01L29/66 ,  H01L27/02 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/1095 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7835

Abstract: A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is substantially disposed over the center of the semiconductor device cell. The SSBC also includes at least one source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC.

Abstract translation: 在碳化硅（SiC）半导体层的表面上制造半导体器件单元的方法包括在SiC半导体层的表面上形成半导体器件单元的分段源极和体接触（SSBC）。 SSBC包括设置在半导体层的表面上并且靠近半导体器件单元的体接触区域的体接触部分，其中主体接触部分基本上设置在半导体器件单元的中心之上。 SSBC还包括设置在半导体层的表面上并且靠近半导体器件单元的源极接触区域的至少一个源极接触部分，其中至少一个源极接触部分仅部分地围绕SSBC的主体接触部分。

公开(公告)号：US20150155355A1

公开(公告)日：2015-06-04

申请号：US14097075

申请日：2013-12-04

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4236 ,  H01L23/544 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7832 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.). A semiconductor device includes a well region extending a first depth into a surface of an epitaxial semiconductor layer positioned above a drift region. The device includes a junction field-effect transistor (JFET) region positioned adjacent to the well region in the epitaxial semiconductor layer. The device also includes a trench extending a second depth into the JFET region, wherein the trench comprises a bottom and a sidewall that extends down to the bottom at an angle relative to the surface of the epitaxial semiconductor layer.

Abstract translation: 本文公开的主题涉及诸如碳化硅（SiC）功率器件（例如，MOSFET，IGBT等）的金属氧化物半导体（MOS）器件。 半导体器件包括将第一深度延伸到位于漂移区上方的外延半导体层的表面的阱区。 该器件包括邻近外延半导体层中的阱区定位的结场效应晶体管（JFET）区域。 该器件还包括将第二深度延伸到JFET区域中的沟槽，其中该沟槽包括底部和与该外延半导体层的表面成一定角度向下延伸到底部的侧壁。

公开(公告)号：US09024328B2

公开(公告)日：2015-05-05

申请号：US13934053

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L21/22 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L21/22 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/7827

Abstract: A semiconductor device includes a silicon carbide (SiC) drift layer disposed on a (0001) oriented SiC substrate. The SiC drift layer has a non-planar surface including a plurality of repeating features that are oriented parallel to a length of a channel of the semiconductor device. Further, the channel region is disposed in a particular crystallographic plane of the SiC drift layer.

Abstract translation: 半导体器件包括设置在（0001）取向的SiC衬底上的碳化硅（SiC）漂移层。 SiC漂移层具有包括平行于半导体器件的沟道的长度定向的多个重复特征的非平面表面。 此外，沟道区设置在SiC漂移层的特定结晶平面中。

公开(公告)号：US20150008446A1

公开(公告)日：2015-01-08

申请号：US13933366

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Stacey Joy Kennerly

IPC: H01L21/04 ,  H01L29/16

CPC classification number: H01L21/046 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7811

Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm−2 to about 12×1013 cm−2. Semiconductor devices are also presented.

Abstract translation: 提出了制造半导体器件的方法。 该方法包括提供包括碳化硅的半导体层，其中半导体层包括掺杂有第一掺杂剂类型的第一区域。 该方法还包括使用单个注入掩模和基本相似的注入剂量来注入具有第二掺杂剂类型的半导体层，以在半导体层中形成第二区域和结终止延伸（JTE），其中注入剂量在一个范围内 从约2×10 13 cm -2至约12×10 13 cm -2。 还提供了半导体器件。

公开(公告)号：US20140159141A1

公开(公告)日：2014-06-12

申请号：US13712188

申请日：2012-12-12

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.

Abstract translation: 绝缘栅场效应晶体管（IGFET）器件包括半导体本体和栅极氧化物。 半导体本体包括掺杂有第一类型掺杂剂的第一阱区域和掺杂有相反电荷的第二类型掺杂剂并位于第一阱区域内的第二阱区域。 栅极氧化物包括具有不同厚度尺寸的外部部分和内部部分。 外部部分设置在半导体本体的第一阱区域和第二阱区域的上方。 内部部分设置在半导体本体的结栅场效应晶体管区域的上方。 半导体本体被配置为当栅极信号施加到设置在栅极氧化物上的栅极触点时，通过第二阱区域和结栅场效应晶体管区域形成导电沟道。