公开(公告)号：US20200335594A1

公开(公告)日：2020-10-22

申请号：US16386545

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Shesh Mani Pandey

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L21/321

Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

公开(公告)号：US20200335435A1

公开(公告)日：2020-10-22

申请号：US16918053

申请日：2020-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US20200312947A1

公开(公告)日：2020-10-01

申请号：US16369788

申请日：2019-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L49/02 ,  H01L29/78 ,  H01L27/088 ,  H01L21/768 ,  H01L21/762 ,  H01L23/522

Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material

公开(公告)号：US10790363B2

公开(公告)日：2020-09-29

申请号：US16054033

申请日：2018-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laertis Economikos ,  Kevin J. Ryan ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/66

Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.

公开(公告)号：US10756184B2

公开(公告)日：2020-08-25

申请号：US16180486

申请日：2018-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Judson R. Holt ,  Steffen A. Sichler ,  Ömür I. Aydin ,  Wei Hong ,  Yi Qi ,  Hui Zang ,  Liu Jiang

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

公开(公告)号：US20200243643A1

公开(公告)日：2020-07-30

申请号：US16256252

申请日：2019-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative integrated circuit product disclosed herein includes a single diffusion break (SDB) isolation structure positioned between a first fin portion and a second fin portion, wherein the first fin portion comprises a first end surface and the second fin portion comprises a second end surface. In this example, the SDB structure includes a conformal liner layer that engages the first end surface of the first fin portion and the second end surface of the second fin portion, an insulating material positioned on the conformal liner layer, a cap structure positioned above an upper surface of the insulating material and an air gap positioned between a bottom surface of the cap structure and the upper surface of the insulating material.

公开(公告)号：US10727136B2

公开(公告)日：2020-07-28

申请号：US16185675

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

公开(公告)号：US10707303B1

公开(公告)日：2020-07-07

申请号：US16264273

申请日：2019-01-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Hui Zang ,  Zhenyu Owen Hu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

Abstract: A semiconductor device, comprising a semiconductor substrate; an isolation layer disposed on the semiconductor substrate; a first active region and a second active region disposed at least partially above the isolation layer; a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region; and an isolation pillar disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation pillar has an inverted-T shape. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device.

公开(公告)号：US10699957B2

公开(公告)日：2020-06-30

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3105

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US10692987B2

公开(公告)日：2020-06-23

申请号：US16164867

申请日：2018-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Guowei Xu ,  Hui Zang

IPC: H01L29/66 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/78

Abstract: The disclosure provides an integrated circuit (IC) structure including a first spacer on a semiconductor fin adjacent a first portion of the gate structure, and having a first height above the semiconductor fin; a second spacer on the semiconductor fin adjacent the first spacer, such that the first spacer is horizontally between the first portion of the gate structure and a lower portion of the outer; and a gate cap positioned over the first portion of the gate structure and on the second spacer above the semiconductor fin. The gate cap defines an air gap horizontally between the first portion of the gate structure and an upper portion of the second spacer, and vertically between an upper surface of the first spacer and a lower surface of the gate cap.