公开(公告)号：US20120249159A1

公开(公告)日：2012-10-04

申请号：US13074407

申请日：2011-03-29

申请人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： G01R31/04 ,  G01R31/02 ,  H01L23/62

CPC分类号： H01L23/5226 ,  G01R31/025 ,  G01R31/04 ,  G01R31/07 ,  G01R31/327 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

摘要： A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

摘要翻译： 线路的后端（BEOL）保险丝结构具有一叠通孔。 通孔的堆叠导致高的纵横比，使得通孔内的衬里和种子覆盖较差。 衬里和种子层的弱点导致电迁移（EM）故障的较高概率。 保险丝结构由于衬垫和种子覆盖不良而解决故障。 设计特征允许确定故障发生的位置，确定熔丝编程之后受损区域的程度，并防止损坏的介质区域的进一步传播。

公开(公告)号：US08026166B2

公开(公告)日：2011-09-27

申请号：US12190131

申请日：2008-08-12

申请人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-sang Oh

发明人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-sang Oh

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.

摘要翻译： 提供包括具有低介电常数和良好氧阻隔性能的封盖层的互连结构及其制备方法。 在一个实施例中，集成电路结构包括：设置在半导体衬底之上的层间电介质层; 嵌入在所述层间电介质层中的导电互连; 包括设置在所述导电互连上的SiwCxNyHz的第一覆盖层; 包含设置在第一覆盖层上的介电常数小于约4的SiaCbNcHd（具有较小的N）的第二覆盖层; 以及第三覆盖层，其包括设置在所述第二覆盖层上的SiwCxNyHz，其中a + b + c + d = 1.0和a，b，c和d各自大于0且小于1，并且其中w + x + y + z = 1.0，w，x，y和z分别大于0且小于1。

公开(公告)号：US20110175226A1

公开(公告)日：2011-07-21

申请号：US12691213

申请日：2010-01-21

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76847 ,  H01L23/522 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line

摘要翻译： 用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分

公开(公告)号：US20110092067A1

公开(公告)日：2011-04-21

申请号：US12972808

申请日：2010-12-20

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

摘要翻译： 在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。 将嵌段聚合物施加到硬掩模层上，自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。 蚀刻硬掩模和低k材料层以形成空腔。 导电材料镀在暴露的金属表面上，包括金属特征的顶表面的部分以形成金属垫。 金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。 进行蚀刻以放大和合并低k材料层中的空腔。 通过金属硅化物焊盘防止金属特征被蚀刻。 形成具有空隙并且没有金属特征表面的缺陷的互连结构。

公开(公告)号：US07884477B2

公开(公告)日：2011-02-08

申请号：US11949189

申请日：2007-12-03

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

摘要翻译： 在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。 将嵌段聚合物施加到硬掩模层上，自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。 蚀刻硬掩模和低k材料层以形成空腔。 导电材料镀在暴露的金属表面上，包括金属特征的顶表面的部分以形成金属垫。 金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。 进行蚀刻以放大和合并低k材料层中的空腔。 通过金属硅化物焊盘防止金属特征被蚀刻。 形成具有空隙并且没有金属特征表面的缺陷的互连结构。

公开(公告)号：US07737528B2

公开(公告)日：2010-06-15

申请号：US12132337

申请日：2008-06-03

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

IPC分类号： H01L21/768

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.

摘要翻译： 用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层; 仅在所述金属互连层的顶表面的一部分上形成的金属盖层; 以及形成在所述金属盖层和所述金属互连层的其余部分上的电介质盖层，其不形成有所述金属盖层; 其中不具有形成在其上的金属覆盖层的金属互连层的其余部分容易受到电迁移故障机制的影响，以便通过施加通过细长金属互连层的电流来编程熔丝结构。

公开(公告)号：US07671470B2

公开(公告)日：2010-03-02

申请号：US12179057

申请日：2008-07-24

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Shyng-Tsong Chen ,  Kelly Malone

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Shyng-Tsong Chen ,  Kelly Malone

IPC分类号： H01L21/461

CPC分类号： H01L23/5226 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

公开(公告)号：US07666753B2

公开(公告)日：2010-02-23

申请号：US11622188

申请日：2007-01-11

申请人： Griselda Bonilla ,  Shyng-Tsong Chen ,  Matthew E. Colburn ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Shyng-Tsong Chen ,  Matthew E. Colburn ,  Chih-Chao Yang

IPC分类号： H01L21/76

CPC分类号： H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact the metal lines. In addition, air gaps are between the metal lines, wherein the air gaps are between the metal caps. A second dielectric is also provided over the bottom portion of a first dielectric, wherein a top portion of the second dielectric is over the metal caps, and wherein top portions of the first dielectric and bottom portions of the second dielectric comprise sides of the air gap. The apparatus further includes dielectric caps over the metal lines, wherein the dielectric caps contact the metal caps.

摘要翻译： 本发明的实施例提供了一种用于具有气隙的BEOL互连的金属封盖工艺。 更具体地，提供了一种包括在第一电介质内的金属线的装置。 金属盖在金属线上方，金属帽与金属线接触。 此外，气隙在金属线之间，其中气隙在金属盖之间。 第二电介质还设置在第一电介质的底部上方，其中第二电介质的顶部在金属帽之上，并且其中第二电介质的第一电介质和底部的顶部包括气隙的侧面 。 该装置还包括金属线上的电介质盖，其中介电帽与金属盖接触。

公开(公告)号：US20100038793A1

公开(公告)日：2010-02-18

申请号：US12190131

申请日：2008-08-12

申请人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-Sang Oh

发明人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-Sang Oh

IPC分类号： H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.

摘要翻译： 提供包括具有低介电常数和良好氧阻隔性能的封盖层的互连结构及其制备方法。 在一个实施例中，集成电路结构包括：设置在半导体衬底之上的层间电介质层; 嵌入在所述层间电介质层中的导电互连; 包括设置在所述导电互连上的SiwCxNyHz的第一覆盖层; 包含设置在第一覆盖层上的介电常数小于约4的SiaCbNcHd（具有较小N）的第二覆盖层; 以及第三覆盖层，其包括设置在所述第二覆盖层上的SiwCxNyHz，其中a + b + c + d = 1.0和a，b，c和d各自大于0且小于1，并且其中w + x + y + z = 1.0，w，x，y和z分别大于0且小于1。

公开(公告)号：US20100038790A1

公开(公告)日：2010-02-18

申请号：US12191534

申请日：2008-08-14

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.

摘要翻译： 一种集成电路，其包括半导体衬底，所述半导体衬底上的包括金属布线的第一金属布线级别，所述第一金属布线层上的互连布线级别，其包括层间电介质内的通孔布线，第二金属布线级别 包括金属布线的互连布线层，至少一个具有多个介电填充形状的金属布线，其减小了所述至少一个金属布线的横截面积，并且其中所述通孔互连使金属线 在第一布线级别和第二布线级中的至少一个金属布线中，通孔布线与多个介质填充形状相邻并间隔开。 还公开了一种方法，其中多个介电填充形状被放置成与第二布线层中的布线中的通孔接触区域相邻并间隔开。