公开(公告)号：US09691878B2

公开(公告)日：2017-06-27

申请号：US14436892

申请日：2012-10-30

申请人： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

发明人： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L29/161

CPC分类号： H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7848

摘要： Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

公开(公告)号：US09263581B2

公开(公告)日：2016-02-16

申请号：US14394802

申请日：2012-05-30

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qingqing Liang

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qingqing Liang

IPC分类号： H01L23/62 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06

CPC分类号： H01L29/7849 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66772 ,  H01L29/78654

摘要： A method for manufacturing a semiconductor structure comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.

摘要翻译： 一种制造半导体结构的方法包括以下步骤：在SOI衬底上提供SOI衬底并形成栅极结构; 通过使用栅极结构作为掩模来注入离子以在半导体结构中引起应力，以形成位于栅极结构两侧的SOI衬底上的BOX层下方的应力诱导区域。 还公开了根据上述方法制造的半导体结构。 在本申请中公开的半导体结构及其制造方法在地层上形成应力诱导区域，其对半导体器件沟道提供有利的应力，有助于提高半导体器件的性能。

公开(公告)号：US09236384B2

公开(公告)日：2016-01-12

申请号：US14355120

申请日：2012-03-22

申请人： Zhijiong Luo ,  Zhengyong Zhu ,  Haizhou Yin ,  Huilong Zhu

发明人： Zhijiong Luo ,  Zhengyong Zhu ,  Haizhou Yin ,  Huilong Zhu

IPC分类号： G11C11/405 ,  G11C5/06 ,  G11C5/02 ,  G11C7/00 ,  H01L27/105 ,  G11C11/404 ,  H01L29/267 ,  H01L29/786 ,  G11C8/16 ,  H01L27/108

CPC分类号： H01L27/1052 ,  G11C5/06 ,  G11C7/00 ,  G11C8/16 ,  G11C11/404 ,  G11C11/405 ,  H01L27/108 ,  H01L29/267 ,  H01L29/7869

摘要： A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.

摘要翻译： 公开了一种半导体存储器件及其访问方法。 半导体存储器件包括存储晶体管，第一控制晶体管和第二控制晶体管，其中第一控制晶体管的源电极和栅电极分别耦合到第一位线和第一字线，漏电极和 第二控制晶体管的栅电极分别耦合到第二字线和第二位线，存储晶体管的栅电极耦合到第一控制晶体管的漏电极，存储晶体管的漏电极耦合 到第二控制晶体管的源电极，并且存储晶体管的源电极耦合到地，并且其中存储晶体管表现出栅电极控制的存储特性。 半导体存储器件增加了集成度并降低了刷新频率。

公开(公告)号：US09178070B2

公开(公告)日：2015-11-03

申请号：US13138053

申请日：2011-03-04

申请人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78648 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78603

摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.

摘要翻译： 本申请公开了一种半导体结构及其制造方法。 根据本发明的半导体结构可以通过在具有公共接触的源极区域或漏极区域之间的电容耦合来调节阈值电压，即源极接触或漏极接触，这导致简单的制造过程 ，更高的集成度，更低的制造成本。 此外，背栅结构的非对称设计以及可以根据实际器件设计中所需而改变的背栅区域的掺杂，可以进一步增强调节阈值电压并提高器件性能的效果。

公开(公告)号：US08969164B2

公开(公告)日：2015-03-03

申请号：US14002456

申请日：2012-03-23

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/51

CPC分类号： H01L29/7842 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/51 ,  H01L29/66431

摘要： A semiconductor structure comprises a substrate, a gate stack, a base area, and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate. A supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate; a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure. A stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure. Correspondingly, a method is provided for manufacturing such a semiconductor structure, which inhibits the short channel effect, reduces the parasitic capacitance and leakage current, and enhances the steepness of the source/drain region.

摘要翻译： 半导体结构包括衬底，栅极堆叠，基极区域和源极/漏极区域，其中栅极堆叠层位于基极区域上，源极/漏极区域位于基极区域中，并且基极区域是 位于基板上。 在基部区域和基板之间设置支撑隔离结构，其中支撑结构的一部分连接到基板; 在基部区域和基板之间设置空腔，其中空腔由基底区域，基底和支撑隔离结构构成。 在栅极堆叠的两侧，基部区域和支撑隔离结构上设置应力材料层。 相应地，提供了一种用于制造这种半导体结构的方法，其抑制短沟道效应，降低寄生电容和漏电流，并且增强源/漏区的陡度。

公开(公告)号：US08828840B2

公开(公告)日：2014-09-09

申请号：US13379546

申请日：2011-04-26

申请人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

发明人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

IPC分类号： H01L21/762 ,  H01L21/02

CPC分类号： H01L21/76232 ,  H01L21/02381 ,  H01L21/02521 ,  H01L21/02639 ,  H01L21/02647

摘要： A semiconductor device and a method for manufacturing the same are disclosed. The method comprises: forming at least one trench in a first semiconductor layer, wherein at least lower portions of respective sidewalls of the trench tilt toward outside of the trench; filling a dielectric material in the trench, thinning the first semiconductor layer so that the first semiconductor layer is recessed with respect to the dielectric material, and epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the semiconductor layer comprise different materials from each other. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.

摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括：在第一半导体层中形成至少一个沟槽，其中沟槽的各个侧壁的至少下部部分朝向沟槽的外侧倾斜; 在沟槽中填充介电材料，使第一半导体层变薄，使得第一半导体层相对于电介质材料凹陷，并且在第一半导体层上外延生长第二半导体层，其中第一半导体层和半导体层 包括彼此不同的材料。 根据本公开的实施例，可以有效地抑制在异质外延生长期间发生的缺陷。

公开(公告)号：US20140238461A1

公开(公告)日：2014-08-28

申请号：US13950510

申请日：2013-07-25

申请人： Zhijiong LUO ,  Huilong ZHU ,  Haizhou Yin

发明人： Zhijiong LUO ,  Huilong ZHU ,  Haizhou Yin

IPC分类号： H01L31/18 ,  H01L31/04

CPC分类号： H01L31/035281 ,  H01L31/042 ,  H01L31/0504 ,  H01L31/1804 ,  H01L31/202 ,  Y02E10/50 ,  Y02E10/547 ,  Y02P70/521

摘要： The present invention provides a solar cell unit, which comprises a semiconductor plate of first-type doping or second-type doping; wherein the semiconductor plate has a first surface and a second surface opposite to the first surface; the semiconductor plate comprises a first-type doping region and second-type doping region, both the first-type doping region and the second-type doping region are located on the first surface of the semiconductor plate; a first sheet is provided on the side surface of the semiconductor plate that is adjacent to the first-type doping region, and a second sheet is provided on the side surface of the semiconductor plate that is adjacent to the second type doping region.

摘要翻译： 本发明提供一种太阳能电池单元，其包括第一种掺杂或二次掺杂的半导体板; 其中所述半导体板具有与所述第一表面相对的第一表面和第二表面; 所述半导体板包括第一类型掺杂区域和第二类型掺杂区域，所述第一类型掺杂区域和所述第二类型掺杂区域都位于所述半导体板件的所述第一表面上; 第一片设置在与第一型掺杂区相邻的半导体板的侧表面上，并且第二片设置在与第二类型掺杂区相邻的半导体板的侧表面上。

公开(公告)号：US08766371B2

公开(公告)日：2014-07-01

申请号：US13256866

申请日：2011-02-25

申请人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L21/70

CPC分类号： H01L29/4983 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/7845

摘要： There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region.

摘要翻译： 提供半导体结构及其制造方法。 根据本发明的半导体结构包括：半导体衬底; 形成在半导体衬底上的沟道区; 形成在沟道区上的栅叠层; 以及形成在沟道区两侧并嵌入在半导体衬底中的源/漏区。 栅极堆叠包括：形成在沟道区上的栅极电介质层; 以及位于栅介质层上的导电层。 对于nMOSFET，导电层具有将压应力施加到沟道区的压应力; 并且对于pMOSFET，导电层具有拉伸应力以向沟道区域施加压应力。

公开(公告)号：US08754503B2

公开(公告)日：2014-06-17

申请号：US13355946

申请日：2012-01-23

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L27/1218

摘要： The present invention provides a strip plate structure and a method for manufacturing the same. The strip plate structure comprises a strip plate array, which comprises a plurality of strip plates arranged with spacing in a predetermined direction on a same plane, wherein each of the strip plates has a first surface and a second surface opposite to the first surface and the strip plate array is arranged on a plane parallel to the first surface of the strip plates; a plurality of strip sheets which connect neighboring ones of the strip plates; flexible material layers, which are located on at least a portion of the surfaces of the strip sheets and/or on at least a portion of the surfaces of the strip plates.

摘要翻译： 本发明提供一种带状板结构及其制造方法。 带状板结构包括条板阵列，其包括在同一平面上以预定方向间隔布置的多个带状板，其中每个带状板具有第一表面和与第一表面相对的第二表面， 带板阵列布置在平行于带状板的第一表面的平面上; 多个带状片，其连接相邻的条板; 柔性材料层位于带状片的至少一部分表面上和/或在带状板的至少一部分表面上。

公开(公告)号：US08674449B2

公开(公告)日：2014-03-18

申请号：US13576550

申请日：2011-11-25

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L21/70 ,  H01L27/088

CPC分类号： H01L29/785 ,  H01L27/0924 ,  H01L29/66795

摘要： A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.

摘要翻译： 公开了一种半导体器件及其制造方法。 在一个实施例中，半导体器件可以包括半导体层，通过图案化半导体层形成的鳍和跨在翅片上的栅极堆叠。 鳍可以在其底部包括掺杂块区域。 根据本实施方式，能够通过块区域有效地抑制翅片底部的电流泄漏。