Indium recovery method
    72.
    发明授权
    Indium recovery method 有权
    铟回收法

    公开(公告)号:US09435008B2

    公开(公告)日:2016-09-06

    申请号:US14126835

    申请日:2012-08-09

    摘要: According to the present invention, there is provided an indium recovery method for recovering indium from an indium-containing product, including a leaching step of allowing indium to leach into an aqueous hydrochloric acid solution by hydrothermal leaching using the aqueous hydrochloric acid solution as a leaching agent from the indium-containing product to obtain a leachate composed of an aqueous hydrochloric acid solution containing indium, and a separating step of adding a microbe for adsorbing In ions to the leachate to separate indium from the leachate.

    摘要翻译: 根据本发明,提供了一种用于从含铟产品中回收铟的铟回收方法,包括使用盐酸水溶液作为浸出使铟浸出到盐酸水溶液中的浸出步骤 得到由含有铟的盐酸水溶液组成的浸出液的分离步骤,以及将浸出液中的In离子添加到分离步骤中,以将铟离子从浸出液中分离出来。

    INDIUM RECOVERY METHOD
    73.
    发明申请
    INDIUM RECOVERY METHOD 有权
    印度回收方法

    公开(公告)号:US20140144292A1

    公开(公告)日:2014-05-29

    申请号:US14126835

    申请日:2012-08-09

    IPC分类号: C22B58/00

    摘要: According to the present invention, there is provided an indium recovery method for recovering indium from an indium-containing product, including a leaching step of allowing indium to leach into an aqueous hydrochloric acid solution by hydrothermal leaching using the aqueous hydrochloric acid solution as a leaching agent from the indium-containing product to obtain a leachate composed of an aqueous hydrochloric acid solution containing indium, and a separating step of adding a microbe for adsorbing In ions to the leachate to separate indium from the leachate.

    摘要翻译: 根据本发明,提供了一种用于从含铟产品中回收铟的铟回收方法,包括使用盐酸水溶液作为浸出使铟浸出到盐酸水溶液中的浸出步骤 得到由含有铟的盐酸水溶液组成的浸出液的分离步骤,以及将浸出液中的In离子添加到分离步骤中,以将铟离子从浸出液中分离出来。

    VEHICLE NAVIGATION DEVICE
    74.
    发明申请
    VEHICLE NAVIGATION DEVICE 审中-公开
    车辆导航装置

    公开(公告)号:US20100057347A1

    公开(公告)日:2010-03-04

    申请号:US12548842

    申请日:2009-08-27

    IPC分类号: G01C21/36

    CPC分类号: G01C21/3611 G01C21/3679

    摘要: A vehicle navigation device including a destination setting means that sets a destination; a route searching means that searches for a route to the destination that has been set by the destination setting means; and a search condition setting means that sets a specified search condition from a plurality of conditions that include a type of facility serving as a search object and an area serving as a search object, in which the route searching means, in the case of an input operation of a specified search condition being performed by the user, searches for a waypoint and a route thereof based on the search condition.

    摘要翻译: 一种车辆导航装置,包括设置目的地的目的地设定装置; 路径搜索单元,搜索由目的地设定单元设定的到目的地的路线; 以及搜索条件设置装置,其从包括用作搜索对象的设施的类型和用作搜索对象的区域的多个条件设置指定的搜索条件,其中路径搜索装置在输入的情况下 由用户执行指定搜索条件的操作,基于搜索条件搜索路线点和路线。

    Communication Apparatus
    75.
    发明申请
    Communication Apparatus 失效
    通讯设备

    公开(公告)号:US20080273542A1

    公开(公告)日:2008-11-06

    申请号:US11885942

    申请日:2006-03-20

    IPC分类号: H04L12/56 H04J3/24

    摘要: A communication apparatus according to the invention can be applied to constitute each of relay nodes provided to constitute a novel communication network which avoids electric wave collision arising on a communication channel without carrying out “carrier sense” or operations for transmitting and receiving control information, such as “RTS”, “CTS”, and so no. The communication apparatus comprises a temporary managing portion 16 for controlling temporary memory means 15, a main managing portion 18 for controlling main memory means 17 and an operation control portion 20. The operation control portion 20 is operative to cause the temporary managing portion 16 and the main managing portion 18 to utilize the state information or the history and state information for obtaining probability of deletion or transmission and probability of delay with regard to each data frame of framed data for discharge and to control, on the basis of the obtained probability of deletion or transmission and the obtained probability of delay, deletion or transmission of the data frame of the framed data for discharge and delay for transmission of the data frame of the framed data for discharge on the occasion of the transmission thereof.

    摘要翻译: 根据本发明的通信装置可以应用于构成每个中继节点,以构成新的通信网络,以避免在通信信道上产生的电波冲突而不执行“载波侦听”或用于发送和接收控制信息的操作,例如 作为“RTS”,“CTS”等等。 通信装置包括用于控制临时存储装置15的临时管理部分16,用于控制主存储装置17的主管理部分18和操作控制部分20。 操作控制部分20用于使临时管理部分16和主管理部分18利用状态信息或历史和状态信息来获得删除或发送的概率以及关于帧的每个数据帧的延迟概率 基于所获得的删除或传输的概率以及所获得的用于放电的成帧数据的数据帧的延迟,删除或传输的概率以及用于发送成帧数据的数据帧的延迟的数据 用于在其传输时进行放电。

    Operating device
    76.
    发明授权
    Operating device 有权
    操作装置

    公开(公告)号:US07436398B2

    公开(公告)日:2008-10-14

    申请号:US10787769

    申请日:2004-02-27

    IPC分类号: G09G5/00

    摘要: An operating device for controlling a display screen, which includes a rotatable operating member of cylindrical shape, and a slidable operating member having a cylindrical tip portion located above an upper end of the rotatable operating member. The diameter of an upper surface of the slidable operating member cylindrical tip portion is reduced relative to a diameter of a lower surface of the cylindrical tip portion, and the diameter of the lower surface of the slidable operating member cylindrical tip portion is equal to or less than a diameter of an upper surface of the rotatable operating member. An operating device is provided which prevents a misoperation in slide operation and rotation operation and improves operability.

    摘要翻译: 一种用于控制显示屏幕的操作装置,其包括圆柱形形状的可旋转操作构件,以及具有位于可旋转操作构件的上端上方的圆柱形末端部分的可滑动操作构件。 可滑动操作构件圆柱形末端部分的上表面的直径相对于圆柱形末端部分的下表面的直径减小,并且可滑动操作构件圆柱形尖端部分的下表面的直径等于或小于 比可旋转操作构件的上表面的直径大。 提供一种操作装置,其防止滑动操作和旋转操作中的误操作,并提高可操作性。

    Synchronous semiconductor memory device in which current consumed by
input buffer circuit is reduced
    77.
    发明授权
    Synchronous semiconductor memory device in which current consumed by input buffer circuit is reduced 失效
    同步半导体存储器件,其中由输入缓冲电路消耗的电流减小

    公开(公告)号:US5880998A

    公开(公告)日:1999-03-09

    申请号:US960268

    申请日:1997-10-29

    摘要: An external clock enable signal is taken in accordance with a first internal clock signal from clock buffer circuit from which an input buffer enable signal is generated to be input to input buffer circuit. Current path in the input buffer circuit is shut off in accordance with the input buffer enable signal. Since the state of the input buffer enable signal is changed in synchronization with the rise of the internal clock signal, the set up time of the external signal can be sufficiently ensured while current consumption of input buffer circuit can be reduced.

    摘要翻译: 根据来自时钟缓冲器电路的第一内部时钟信号,产生外部时钟使能信号,从其产生输入缓冲器使能信号以输入到输入缓冲器电路。 根据输入缓冲器使能信号,输入缓冲器电路中的电流路径被切断。 由于输入缓冲器使能信号的状态与内部时钟信号的上升同步地改变,所以可以充分确保外部信号的建立时间,同时可以减少输入缓冲电路的消耗电流。

    Semiconductor memory cell for holding data with small power consumption
    78.
    发明授权
    Semiconductor memory cell for holding data with small power consumption 失效
    用于保存具有小功耗的数据的半导体存储单元

    公开(公告)号:US5473178A

    公开(公告)日:1995-12-05

    申请号:US223187

    申请日:1994-04-05

    申请人: Yasuhiro Konishi

    发明人: Yasuhiro Konishi

    CPC分类号: H01L27/10808

    摘要: A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

    摘要翻译: DRAM包括在P型半导体衬底的主表面上形成的N型阱,形成在P型半导体衬底的主表面上的N型杂质区,形成在N型杂质区中的N型杂质区 型是存储电容器的存储节点,以及用于连接P型杂质区域和N型杂质区域的多晶硅层。 N型杂质层,P型杂质层和多晶硅层构成存储电容器的存储节点,并且从衬底流到N型杂质层的少数载流子的电子与从 N型阱到P型杂质层。

    Power-on reset signal generator and operating method thereof
    79.
    发明授权
    Power-on reset signal generator and operating method thereof 失效
    上电复位信号发生器及其操作方法

    公开(公告)号:US5469099A

    公开(公告)日:1995-11-21

    申请号:US45387

    申请日:1993-04-13

    申请人: Yasuhiro Konishi

    发明人: Yasuhiro Konishi

    IPC分类号: G06F1/24 H03K17/22 H03K5/13

    CPC分类号: G06F1/24 H03K17/223

    摘要: A first signal generation circuit generates a signal which rises from the ground level to a second level when a prescribed time elapses after an external supply potential starts to rise from the ground level to a first level. A second signal generation circuit outputs a power-on reset signal which falls when the signal outputted from the first signal generation circuit exceeds a first prescribed level and an internal supply potential for an internal circuit outputted from internal supply potential generation means exceeds a second prescribed level.

    摘要翻译: 第一信号发生电路在外部电源电位从地电平开始上升到第一电平之后经过规定时间时,产生从地电平上升到第二电平的信号。 第二信号发生电路输出当从第一信号发生电路输出的信号超过第一规定电平时下降的上电复位信号,并且从内部供电电位产生装置输出的内部电路的内部电源电压超过第二规定电平 。

    Semiconductor memory device divided into blocks and operable to read and
write data through different data lines and operation method of the same
    80.
    发明授权
    Semiconductor memory device divided into blocks and operable to read and write data through different data lines and operation method of the same 失效
    半导体存储器件分为多个块,可操作用于通过不同的数据线读取和写入数据及其操作方法

    公开(公告)号:US5289431A

    公开(公告)日:1994-02-22

    申请号:US952929

    申请日:1992-09-29

    申请人: Yasuhiro Konishi

    发明人: Yasuhiro Konishi

    CPC分类号: G11C11/409 G11C11/4094

    摘要: In a DRAM of separated I/O type, column selecting lines for reading data and column selecting lines for writing data are provided independently from each other. An addition circuit is provided corresponding to each memory cell array block for precharging, when that memory cell array is not selected, a read line pair corresponding that memory cell array block to the same potential Vb1 as that of the bit lines equalized by an equalizer circuit. Both in data reading and writing operations, current does not flow between any equalizer circuit and the write data line pair provided corresponding to each unselected memory cell array block in spite of the fact that a transistor for write selection is not provided in each bit line pair.

    摘要翻译: 在分离的I / O型的DRAM中,独立地提供用于读取数据的列选择线和用于写入数据的列选择线。 对应于每个用于预充电的存储单元阵列块提供加法电路,当没有选择该存储单元阵列时,将与该存储单元阵列块相对应的读线对与由均衡电路均衡的位线相同的电位Vb1 。 在数据读取和写入操作中,尽管在每个位线对中没有提供用于写入选择的晶体管的事实,但是在任何均衡器电路和与每个未选择的存储单元阵列块相对应的写入数据线对之间,电流不会流动 。