利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

95 条记录 (耗时 0.046 秒)

    Synchronous semiconductor memory device in which current consumed by input buffer circuit is reduced
    1.
    发明授权
    Synchronous semiconductor memory device in which current consumed by input buffer circuit is reduced 失效
    同步半导体存储器件，其中由输入缓冲电路消耗的电流减小

    公开(公告)号：US5880998A

    公开(公告)日：1999-03-09

    申请号：US960268

    申请日：1997-10-29

    申请人： Masaaki Tanimura ,  Yasuhiro Konishi

    发明人： Masaaki Tanimura ,  Yasuhiro Konishi

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/417 ,  G11C7/00

    CPC分类号： G11C7/1093 ,  G11C11/4082 ,  G11C11/4093 ,  G11C7/1072 ,  G11C7/1078

    摘要： An external clock enable signal is taken in accordance with a first internal clock signal from clock buffer circuit from which an input buffer enable signal is generated to be input to input buffer circuit. Current path in the input buffer circuit is shut off in accordance with the input buffer enable signal. Since the state of the input buffer enable signal is changed in synchronization with the rise of the internal clock signal, the set up time of the external signal can be sufficiently ensured while current consumption of input buffer circuit can be reduced.

    摘要翻译： 根据来自时钟缓冲器电路的第一内部时钟信号，产生外部时钟使能信号，从其产生输入缓冲器使能信号以输入到输入缓冲器电路。 根据输入缓冲器使能信号，输入缓冲器电路中的电流路径被切断。 由于输入缓冲器使能信号的状态与内部时钟信号的上升同步地改变，所以可以充分确保外部信号的建立时间，同时可以减少输入缓冲电路的消耗电流。

    Semiconductor memory device with an internal voltage generating circuit
    5.
    发明授权
    Semiconductor memory device with an internal voltage generating circuit 失效
    具有内部电压发生电路的半导体存储器件

    公开(公告)号：US06333873B1

    公开(公告)日：2001-12-25

    申请号：US08942692

    申请日：1997-09-29

    申请人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Kouji Hayano

    发明人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Kouji Hayano

    IPC分类号： G11C700

    CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C5/146 ,  G11C11/005

    摘要： A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.

    摘要翻译： 半导体存储器件接收独立于对存储器件的访问而重复产生的外部控制信号。 存储器件包括用于响应于控制信号产生期望的内部电压的内部电压发生器。 内部电压发生器包括响应于控制信号的电荷泵电路。 内部电压可以提供诸如衬底偏置电压的负电压，或者可以是在工作电源电压上升压的正电压并且用作升压的字线驱动信号。 该方案消除了用于向电荷泵电路产生重复时钟信号的振荡器，导致半导体存储器件的电流消耗降低和芯片面积减小。

    Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein
    6.
    发明授权
    Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein 有权
    允许在其中令人满意地重写数据的同步半导体存储器件

    公开(公告)号：US06292429B1

    公开(公告)日：2001-09-18

    申请号：US09514370

    申请日：2000-02-28

    申请人： Kiyohiro Furutani ,  Yasuhiro Konishi

    发明人： Kiyohiro Furutani ,  Yasuhiro Konishi

    IPC分类号： G11C800

    CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076

    摘要： In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.

    摘要翻译： 在SDRAM中，在读出放大器激活信号变为高电平之后经过预定时间段后引入控制信号变为有效低电平。 当突发期间的信号变为高电平，并且控制信号也变低时，字线被丢弃，未选择为低电平。 这样，成对的位线可以具有充分放大的电位差，以使数据能够令人满意地重写到存储单元中。

    Synchronous semiconductor memory device reliably fetching external signal in synchronization with clock signal periodically supplied from the exterior
    7.
    发明授权
    Synchronous semiconductor memory device reliably fetching external signal in synchronization with clock signal periodically supplied from the exterior 失效
    同步半导体存储器件与从外部周期性提供的时钟信号同步地可靠地取得外部信号

    公开(公告)号：US5844859A

    公开(公告)日：1998-12-01

    申请号：US923689

    申请日：1997-09-04

    申请人： Hisashi Iwamoto ,  Yasuhiro Konishi

    发明人： Hisashi Iwamoto ,  Yasuhiro Konishi

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/22

    摘要： When an operating frequency is increased and a CAS latency is set longer, a data write end time is delayed by a specific time in response to the change of the CAS latency. The specific time is greater than a period corresponding to the CAS latency. The specific time may be the minimum time necessary for writing second-bit data. The write margin can also be enlarged by delaying the write timing (activation and inactivation) in the interior of a memory itself by one clock cycle of an external clock signal. Thus, a write period for second-bit data is ensured in an SDRAM, even if the operation frequency is increased.

    摘要翻译： 当操作频率增加并且CAS延迟设置得更长时，响应于CAS延迟的改变，数据写入结束时间被延迟特定时间。 具体时间大于对应于CAS延迟的周期。 具体时间可以是写入第二位数据所需的最短时间。 也可以通过将外部时钟信号的一个时钟周期延迟存储器本身内部的写入定时（激活和去激活）来扩大写入裕度。 因此，即使操作频率增加，也可以在SDRAM中确保第二位数据的写周期。

    Multi-bank synchronous semiconductor memory device
    8.
    发明授权
    Multi-bank synchronous semiconductor memory device 失效
    多组同步半导体存储器件

    公开(公告)号：US5764584A

    公开(公告)日：1998-06-09

    申请号：US900650

    申请日：1997-07-25

    申请人： Takahiko Fukiage ,  Mikio Sakurai ,  Yasuhiro Konishi

    发明人： Takahiko Fukiage ,  Mikio Sakurai ,  Yasuhiro Konishi

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C7/103 ,  G11C7/1072

    摘要： A read register and a data transfer circuit are provided to implement two separate data transfer paths with respect to a preamplifier, for alternately transferring data through these two paths. Thus, the data can be transferred with no data collision in each clock cycle. The data are transferred at a high speed every clock cycle regardless of the bank number and the CAS latency in a multi-bank synchronous memory device.

    摘要翻译： 提供读寄存器和数据传输电路以实现关于前置放大器的两个单独的数据传输路径，用于通过这两个路径交替地传送数据。 因此，可以在每个时钟周期内数据传输而没有数据冲突。 数据在每个时钟周期以高速传输，而不管多行同步存储器件中的存储体号和CAS延迟。

    Synchronous type semiconductor memory device operating in synchronization with an external clock signal
    9.
    发明授权
    Synchronous type semiconductor memory device operating in synchronization with an external clock signal 失效
    与外部时钟信号同步工作的同步型半导体存储器件

    公开(公告)号：US5404338A

    公开(公告)日：1995-04-04

    申请号：US189247

    申请日：1994-01-31

    申请人： Yasumitsu Murai ,  Hisashi Iwamoto ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

    发明人： Yasumitsu Murai ,  Hisashi Iwamoto ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

    IPC分类号： G11C11/407 ,  F02B75/02 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C7/222 ,  G11C7/1072 ,  F02B2075/027

    摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

    摘要翻译： 在同步半导体存储器件中，形成激活单元的存储器阵列（MA）被分成多个小存储器阵列（MK）。 提供了两个小型存储器阵列的本地I / O线对（LIO）。 跨字线的全局I / O线对（GIO）排列在字线分流区（WS）中。 连接开关（BS）布置在本地I / O线对与全局I / O线对之间的交叉中。 激活的存储器阵列中的每个小存储器阵列通过本地I / O线对连接到相应的全局I / O线对。 从而，可以同时读取多个比特，而不增加互连占用的面积。 使用读出放大器激活信号进行连接开关的控制。 数据传输到为数据输出端子提供的读数据寄存器用于顺序数据输出或选择存储单元时，全局I / O线被预充电/均衡。 外部时钟信号被分频以产生用于通过充电操作产生内部电压的相移内部时钟信号。

    Synchronous semiconductor memory device
    10.
    发明授权
    Synchronous semiconductor memory device 失效
    同步半导体存储器件

    公开(公告)号：US5384745A

    公开(公告)日：1995-01-24

    申请号：US46333

    申请日：1993-04-14

    申请人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

    发明人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

    IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12

    摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.

    摘要翻译： 存储器阵列被分成可以相互独立操作的存储体。 为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。 存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。 全局IO线连接到前置放大器组并写入缓冲组。 通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止对所需位的写入，如果数据写入应当是数据写入时，可以将数据集中写入所选存储单元 在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。 提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。