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    FORKSHEET TRANSISTORS WITH DIELECTRIC OR CONDUCTIVE SPINE
    73.
    发明申请
    FORKSHEET TRANSISTORS WITH DIELECTRIC OR CONDUCTIVE SPINE 有权

    公开(公告)号：US20220093647A1

    公开(公告)日：2022-03-24

    申请号：US17030226

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

    IPC: H01L27/12 ,  H01L21/84

    Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

    SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING BI-LAYER SEMICONDUCTING OXIDES IN SOURCE AND DRAIN FOR LOW ACCESS AND CONTACT RESISTANCE OF THIN FILM TRANSISTORS
    75.
    发明申请
    SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING BI-LAYER SEMICONDUCTING OXIDES IN SOURCE AND DRAIN FOR LOW ACCESS AND CONTACT RESISTANCE OF THIN FILM TRANSISTORS 审中-公开

    公开(公告)号：US20200066912A1

    公开(公告)日：2020-02-27

    申请号：US16325164

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Gilbert DEWEY ,  Van H. LE ,  Rafael RIOS ,  Shriram SHIVARAMAN ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC

    IPC: H01L29/786 ,  H01L29/221 ,  H01L29/66

    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors. For instance, there is disclosed in accordance with one embodiment a semiconductor device having therein a substrate; a bi-layer oxides layer formed from a first oxide material and a second oxide material, the first oxide material comprising a semiconducting oxide material and having different material properties from the second oxide material comprising a high mobility oxide material; a channel layer formed atop the substrate, the channel layer formed from the semiconducting oxide material of the bi-layer oxides layer; a high mobility oxide layer formed atop the channel layer, the high conductivity oxide layer formed from the high mobility oxide material of the bi-layer oxides layer; metallic contacts formed atop the high mobility oxide layer; a gate and a gate oxide material formed atop the high mobility oxide layer, the gate oxide material being in direct contact with the high mobility oxide layer; and spacers separating the metallic contacts from the gate and gate oxide material. Other related embodiments are disclosed.

    GALLIUM NITRIDE TRANSISTOR WITH UNDERFILL ALUMINUM NITRIDE FOR IMPROVED THERMAL AND RF PERFORMANCE
    76.
    发明申请
    GALLIUM NITRIDE TRANSISTOR WITH UNDERFILL ALUMINUM NITRIDE FOR IMPROVED THERMAL AND RF PERFORMANCE 审中-公开

    公开(公告)号：US20200066848A1

    公开(公告)日：2020-02-27

    申请号：US16074377

    申请日：2016-04-01

    Applicant: Intel Corporation

    Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Paul B. FISCHER

    IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/423

    Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

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