公开(公告)号：US20150084128A1

公开(公告)日：2015-03-26

申请号：US14036158

申请日：2013-09-25

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Qizhi Liu ,  Zhenzhen Ye ,  Yan Zhang

IPC: H01L23/34 ,  H01L21/283

CPC classification number: H01L23/34 ,  H01L21/283 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/367 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures.

Abstract translation: 公开了包括具有局部散热器的SOI器件（例如，SOI金属氧化物半导体场效应晶体管（MOSFET））的绝缘体上半导体（SOI）结构。 每个散热器包括与SOI器件的有源区相邻的开口，该开口延伸穿过SOI器件位于半导体衬底下面的绝缘体层，并且至少部分地填充有填充材料。 该填充材料是导热体，以散发由SOI器件产生的热量，并且也是电隔离器，以便最小化电流泄漏。 在MOSFET的情况下，局部散热器可以在源极/漏极延伸部分或源极/漏极之下对准。 或者，局部散热器可以在通道下方对准或平行并邻近通道的相对侧。 本文还公开了形成这些SOI结构的方法。

公开(公告)号：US20150008559A1

公开(公告)日：2015-01-08

申请号：US14496242

申请日：2014-09-25

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  G06F17/50 ,  H01L29/06

CPC classification number: H01L29/66303 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/7322 ,  H01L29/735

Abstract: Bipolar junction transistors and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.

Abstract translation: 双极结晶体管和双极结晶体管的设计结构。 双极结晶体管可以包括布置在不同的发射极指中的多个发射极。 形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。 发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。 发射极延伸通过外部基极层和硅化物层与本征基极层接触。 发射器可以在替代型工艺中使用牺牲发射器基座形成。

公开(公告)号：US08927379B2

公开(公告)日：2015-01-06

申请号：US13627179

申请日：2012-09-26

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  Kevin K. Chan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L21/8228

CPC classification number: H01L29/7371 ,  H01L21/82285 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.

公开(公告)号：US20140327106A1

公开(公告)日：2014-11-06

申请号：US13887640

申请日：2013-05-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qizhi Liu

IPC: H01L21/762 ,  H01L29/73 ,  H01L29/66

CPC classification number: H01L29/735 ,  G06F17/5045 ,  H01L21/76224 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/1008 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/73

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A semiconductor material layer is formed on a substrate and a mask layer is formed on the semiconductor material layer. The mask layer is patterned to form a plurality of openings to the semiconductor material layer. After the mask layer is formed and patterned, the semiconductor material layer is etched at respective locations of the openings to define a first trench, a second trench separated from the first trench by a first section of the semiconductor material layer defining a terminal of the bipolar junction transistor, and a third trench separated from the first trench by a second section of the semiconductor material layer defining an isolation pedestal. A trench isolation region is formed at a location in the substrate that is determined at least in part using the isolation pedestal as a positional reference.

Abstract translation: 双极结型晶体管的器件结构，制造方法和设计结构。 在基板上形成半导体材料层，在半导体材料层上形成掩模层。 图案化掩模层以形成到半导体材料层的多个开口。 在掩模层形成和图案化之后，半导体材料层在开口的相应位置被蚀刻以限定第一沟槽，第二沟槽通过半导体材料层的第一部分与第一沟槽分开，该第一部分限定了双极的端子 以及通过半导体材料层的限定隔离基座的第二部分与第一沟槽分离的第三沟槽。 在衬底中的至少部分地使用隔离基座作为位置参考确定的位置处形成沟槽隔离区域。

公开(公告)号：US08796149B1

公开(公告)日：2014-08-05

申请号：US13769500

申请日：2013-02-18

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

IPC: H01L21/311

CPC classification number: H01L29/7371 ,  H01L29/0649 ,  H01L29/267 ,  H01L29/66242 ,  H01L29/7327 ,  H01L29/737 ,  H01L29/7378

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 在衬底中限定的器件区域中形成发射极。 在发射极上形成一个本征基极。 形成了通过内在基极与发射极分离的集电极。 集电体包括具有大于器件区域的半导体材料的电子带隙的电子带隙的半导体材料。

公开(公告)号：US20140131773A1

公开(公告)日：2014-05-15

申请号：US14162256

申请日：2014-01-23

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC: H01L29/737

CPC classification number: H01L29/737 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, filling the respective slot.

Abstract translation: 公开了一种自对准双极晶体管及其制造方法。 在一个实施例中，提供衬底和本征基极，随后是第一氧化物层，以及在第一氧化物层上的外部基极。 形成第一开口，暴露外部基底的表面的一部分。 在第一开口中形成侧壁间隔物，并且在外基的暴露表面上选择性地形成自对准氧化物掩模。 去除间隔物，并且使用自对准氧化物掩模，暴露的非本征基底和第一氧化物层被蚀刻以暴露本征基底层，形成第一和第二狭槽。 在第一和第二槽中的每一个中的暴露的固有和/或非本征基层上选择性地生长硅层条纹，填充相应的槽。

公开(公告)号：US20140117493A1

公开(公告)日：2014-05-01

申请号：US13661359

申请日：2012-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peng Cheng ,  Peter B. Gray ,  Vibhor Jain ,  Robert K. Leidy ,  Qizhi Liu

IPC: H01L29/732 ,  G06F17/50 ,  H01L21/331

CPC classification number: H01L29/732 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66242 ,  H01L29/7378

Abstract: Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

Abstract translation: 用于制造器件结构的方法，以及用于双极结型晶体管的器件结构和设计结构。 器件结构包括衬底中的集电极区域，延伸到衬底中并由电绝缘体构成的多个隔离结构以及衬底中的隔离区域。 隔离结构具有长度并且以横向于长度的间距布置，使得每个相邻的一对隔离结构被基板的相应部分分开。 隔离区域通过集电区域的第一部分与隔离结构中的至少一个横向分离。 隔离区域将收集区域的第二部分与收集器区域的第一部分横向分离。 器件结构还包括在集电极区域的第二部分上的本征基极和在本征基极上的发射极。 发射极相对于隔离结构的长度具有横向定向的长度。

公开(公告)号：US08652919B2

公开(公告)日：2014-02-18

申请号：US13740673

申请日：2013-01-14

Applicant: International Business Machines Corporation

Inventor： David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Ramana M. Malladi

IPC: H01L21/331

CPC classification number: H01L29/73 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732

Abstract: Embodiments of the present invention include a method for forming a tunable semiconductor device. In one embodiment, the method comprises: forming a semiconductor substrate; patterning a first mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector; removing the first mask; patterning a second mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector; removing the second mask; and forming a single continuous collector above the second discontinuous subcollector.

Abstract translation: 本发明的实施例包括形成可调谐半导体器件的方法。 在一个实施例中，该方法包括：形成半导体衬底; 在半导体衬底上图案化第一掩模; 所述半导体衬底的掺杂区域不被所述第一掩模保护以形成第一不连续子集电极; 去除第一个面罩; 在半导体衬底上图案化第二掩模; 所述半导体衬底的掺杂区域不被所述第二掩模保护并且在所述第一不连续子集电极的顶部上以形成第二不连续子集电极; 去除第二个掩模; 以及在第二不连续子集电极上方形成单个连续集电器。

公开(公告)号：US20130334664A1

公开(公告)日：2013-12-19

申请号：US13971982

申请日：2013-08-21

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Peng Cheng ,  Qizhi Liu ,  Ljubo Radic

IPC: H01L29/73 ,  G06F17/50

CPC classification number: H01L29/73 ,  G06F17/5045 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7371

Abstract: Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.

Abstract translation: 制造双极结型晶体管，双极结型晶体管以及双极结型晶体管的设计结构的方法。 本征基底层的第一部分被掩蔽，同时蚀刻本征基底层的第二部分。 作为掩蔽的结果，本征基底层的第二部分比本征基底层的第一部分薄。 在与本征基层的第一和第二部分分别的接触关系中形成发射极和非本征基层。

公开(公告)号：US20130147017A1

公开(公告)日：2013-06-13

申请号：US13758204

申请日：2013-02-04

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Peter B. Gray ,  David L. Harame ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu

IPC: H01L29/73

CPC classification number: H01L29/73 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/66272 ,  H01L29/7322

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.