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公开(公告)号：US20160197072A1
公开(公告)日：2016-07-07
申请号：US15073100
申请日：2016-03-17
发明人： Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh , Kejia Wang , Daniel Chanemougame
IPC分类号： H01L27/088 , H01L29/161 , H01L29/06
CPC分类号： H01L27/0886 , H01L21/845 , H01L27/1211 , H01L29/0649 , H01L29/161 , H01L29/66795
摘要： A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.
摘要翻译： 一种半导体器件，包括：衬底; 在第一半导体材料的衬底上方的第一组鳍; 在衬底上方的第二组鳍和不同于第一半导体材料的第二半导体材料; 以及位于所述第一和第二组翅片之间的隔离区域，所述隔离区域具有氮化物层。 隔离区可以是隔离柱或隔离沟槽。
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72.发明授权Buried source-drain contact for integrated circuit transistor devices and method of making same 有权集成电路晶体管器件的埋地源极 - 漏极接触及其制作方法公开(公告)号：US09385201B2
公开(公告)日：2016-07-05
申请号：US14297822
申请日：2014-06-06
发明人： Qing Liu , Ruilong Xie , Chun-Chen Yeh , Xiuyu Cai , William J. Taylor
IPC分类号： H01L21/84 , H01L29/417 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823475 , H01L21/28518 , H01L21/823418 , H01L21/823431 , H01L21/845 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L29/785
摘要： An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.
摘要翻译： 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。
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公开(公告)号：US20160190314A1
公开(公告)日：2016-06-30
申请号：US14588318
申请日：2014-12-31
发明人： Qing Liu , Xiuyu Cai , Chun-chen Yeh , Ruilong Xie
IPC分类号： H01L29/78 , H01L29/423 , H01L21/28 , H01L21/265 , H01L21/266 , H01L29/66 , H01L29/51
CPC分类号： H01L29/7855 , H01L21/26513 , H01L21/266 , H01L21/28141 , H01L29/0653 , H01L29/0657 , H01L29/41783 , H01L29/42356 , H01L29/4236 , H01L29/51 , H01L29/518 , H01L29/66484 , H01L29/66787 , H01L29/66795 , H01L29/66818 , H01L29/7831 , H01L29/785
摘要： A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.
摘要翻译： 垂直狭缝晶体管包括半导体衬底中的凸起的源极，漏极和沟道区。 两个栅极位于半导体衬底的相应侧壁附近。 电介质材料将栅电极与源区和漏区分开。
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公开(公告)号：US20160111513A1
公开(公告)日：2016-04-21
申请号：US14984688
申请日：2015-12-30
发明人： Qing Liu , Ruilong Xie , Chun-chen Yeh , Xiuyu Cai
IPC分类号： H01L29/423 , H01L29/165 , H01L29/06 , H01L29/16 , H01L29/786 , H01L29/66
CPC分类号： H01L29/42392 , B82Y10/00 , H01L29/0649 , H01L29/0673 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/42364 , H01L29/51 , H01L29/518 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/6681 , H01L29/775 , H01L29/785 , H01L29/78618 , H01L29/78696
摘要： A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
摘要翻译： 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是当金属用于形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分发生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。
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75.发明授权公开(公告)号：US09318579B2
公开(公告)日：2016-04-19
申请号：US14300506
申请日：2014-06-10
发明人： Qing Liu , Ruilong Xie , Xiuyu Cai , Kejia Wang , Chun-chen Yeh
CPC分类号： H01L29/66795 , H01L21/28114 , H01L21/32137 , H01L21/32139 , H01L29/66545 , H01L29/6656 , H01L29/7848 , H01L29/785
摘要： A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.
摘要翻译： 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片，以及覆盖半导体鳍片的栅极。 门具有锥形外表面。 在栅极附近形成第一对侧壁间隔物，露出的锥形外表面也被限定。 在露出的锥形外表面上去除栅极的部分以限定凹部。 形成第二对侧壁间隔件，覆盖第一对侧壁间隔件和凹部。 源极/漏极区域形成在半导体鳍片上。
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76.发明授权Method for making semiconductor device with isolation pillars between adjacent semiconductor fins 有权在相邻半导体鳍片之间制造具有隔离柱的半导体器件的方法公开(公告)号：US09281382B2
公开(公告)日：2016-03-08
申请号：US14295618
申请日：2014-06-04
发明人： Qing Liu , Ruilong Xie , Xiuyu Cai , Chun-chen Yeh
CPC分类号： H01L29/66795 , H01L21/76224 , H01L21/823431 , H01L29/0649 , H01L29/6681 , H01L29/785
摘要： A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.
摘要翻译： 制造半导体器件的方法可以包括在衬底之上形成多个横向间隔开的半导体鳍片，以及在横向间隔开的半导体鳍片之间形成第一电介质材料的区域。 该方法还可以包括：从多个半导体鳍片中选择性地移除至少一个中间半导体鳍片，以限定第一介电材料的相应区域之间的至少一个沟槽，以及形成与第一电介质不同的第二电介质材料的区域 所述至少一个沟槽用于在相邻的半导体鳍片之间提供至少一个隔离柱。
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公开(公告)号：US20180090327A1
公开(公告)日：2018-03-29
申请号：US15825409
申请日：2017-11-29
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie
CPC分类号： H01L29/7856 , H01L21/0217 , H01L21/28141 , H01L21/3212 , H01L29/42364 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/785 , H01L29/78654
摘要： A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
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公开(公告)号：US20170194153A1
公开(公告)日：2017-07-06
申请号：US15462657
申请日：2017-03-17
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie
CPC分类号： H01L29/7856 , H01L21/0217 , H01L21/28141 , H01L21/3212 , H01L29/42364 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/785 , H01L29/78654
摘要： Forming a semiconductor structure includes forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps on sides of a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity. The first and second low-k spacer portions are etched. A poly pull process is performed on the remaining portions of the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.
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公开(公告)号：US20170117274A1
公开(公告)日：2017-04-27
申请号：US14920354
申请日：2015-10-22
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66
CPC分类号： H01L29/6653 , H01L21/2018 , H01L21/3065 , H01L21/3081 , H01L21/3086 , H01L21/31053 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/0649 , H01L29/1037 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66795 , H01L29/7853
摘要： Semiconductor devices and methods for making the same includes conformally forming a first spacer on a plurality of fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The plurality of fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.
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80.发明授权公开(公告)号：US09576956B2
公开(公告)日：2017-02-21
申请号：US15157861
申请日：2016-05-18
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L27/088 , H01L27/02 , H01L29/78 , H01L29/66 , H01L29/417 , H01L29/06 , H01L21/336
CPC分类号： H01L27/0886 , H01L27/0207 , H01L29/0649 , H01L29/41791 , H01L29/6656 , H01L29/66795 , H01L29/6681 , H01L29/7848 , H01L29/785
摘要： A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.
摘要翻译： 一种形成包括形成多个半导体柱的半导体器件的方法。 在至少一组相邻的半导体柱之间形成介电间隔物。 半导体材料外延地形成在相邻半导体柱的侧壁上，其中电介质间隔物阻挡形成在第一半导体柱上的外延半导体材料的第一部分与形成在第二半导体柱上的第二部分外延半导体材料合并。
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