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公开(公告)号：US09715385B2
公开(公告)日：2017-07-25
申请号：US13748504
申请日：2013-01-23
CPC分类号： G06F9/30036 , G06F9/3005 , G06F9/30098 , G06F9/3861
摘要： Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.
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公开(公告)号：US09710382B2
公开(公告)日：2017-07-18
申请号：US14485291
申请日：2014-09-12
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/02 , G06F12/0862 , G06F12/1045 , G06F12/1027
CPC分类号： G06F12/0811 , G06F12/0215 , G06F12/0862 , G06F12/1027 , G06F12/1045 , G06F2212/283 , G06F2212/6028 , G06F2212/654
摘要： Hierarchical address translation structures providing separate translations for instruction fetches and data accesses. An address is to be translated from the address to another address using a hierarchy of address translation structures. The hierarchy of address translation structures includes a plurality of levels, and a determination is made as to which level of the plurality of levels it is indicated that translation through the hierarchy of address translation structures is to split into a plurality of translation paths. The hierarchy of address translation structures is traversed to obtain information to be used to translate the address to the another address, in which the traversing selects, based on a determination of the level that indicates the split and based on an attribute of the address to be translated, one translation path of the plurality of translation paths to obtain the information to be used to translate the address to the another address. The information is then used to translate the address to the another address.
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公开(公告)号：US20170193219A1
公开(公告)日：2017-07-06
申请号：US15434254
申请日：2017-02-16
发明人： Michael K. Gschwind
IPC分类号： G06F21/52
CPC分类号： G06F21/6218 , G06F21/53 , G06F2221/033
摘要： Corruption of program stacks is detected by using guard words placed in the program stacks. A called routine executing on a processor checks a guard word in a stack frame of a calling routine. The checking determines whether the guard word has an expected value. Based on determining the guard word has an unexpected value, an indication of corruption of the stack frame is provided. Some routines, however, may not support use of guard words. Thus, routines that are interlinked may have differing protection capabilities. In this situation, a determination may be made as to whether a caller routine supports guard word protection. Based on determining that the caller routine supports guard word protection, the called routine verifies the guard word.
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74.发明申请公开(公告)号：US20170192834A1
公开(公告)日：2017-07-06
申请号：US14989459
申请日：2016-01-06
CPC分类号： G06F11/079 , G06F9/3004 , G06F9/30076 , G06F11/0721 , G06F11/0751
摘要： Corruption of program stacks is detected by using guard words placed in the program stacks. An instruction, which is to be used in protecting stacks of a computing environment, is provided in a called routine, based on determining that the called routine is to include logic to detect corruption of stacks. The instruction in the called routine is to check a guard word provided by a calling routine to determine whether a stack is corrupt.
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公开(公告)号：US09665499B2
公开(公告)日：2017-05-30
申请号：US14993136
申请日：2016-01-12
发明人： Michael K. Gschwind
IPC分类号： G06F12/10 , G06F3/06 , G06F9/455 , G06F12/02 , G06F12/1009 , G06F12/1018 , G06F12/109 , G06F12/1027
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/061 , G06F3/0631 , G06F3/0644 , G06F3/0664 , G06F3/0665 , G06F3/0671 , G06F3/0673 , G06F9/45533 , G06F9/45558 , G06F12/0292 , G06F12/1018 , G06F12/1027 , G06F12/1036 , G06F12/109 , G06F2009/45583 , G06F2212/1016 , G06F2212/151 , G06F2212/657 , G06F2212/7201 , G06F2212/7202
摘要： A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor.
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公开(公告)号：US20170124023A1
公开(公告)日：2017-05-04
申请号：US15401693
申请日：2017-01-09
摘要： A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in another architectural mode of the plurality of architectural modes, wherein the another architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the another architectural mode in place of the one architectural mode restricting use of the one architectural mode.
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公开(公告)号：US09619230B2
公开(公告)日：2017-04-11
申请号：US13931656
申请日：2013-06-28
CPC分类号： G06F9/3802 , G06F9/30054 , G06F9/30058 , G06F9/30145 , G06F9/3016 , G06F9/3806 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based on determining that such an instruction is to be executed, a predicted address is determined for the selected instruction, which is the address to which processing transfers in order to provide the requested services. Then, fetching of instructions beginning at the predicted address prior to execution of the selected instruction is commenced. Further, speculative state relating to a selected instruction, including, for instance, an indication of the privilege level of the selected instruction or instructions executed on behalf of the selected instruction, is predicted and maintained.
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公开(公告)号：US20170097892A1
公开(公告)日：2017-04-06
申请号：US15383306
申请日：2016-12-19
IPC分类号： G06F12/0862 , G06F12/1009
CPC分类号： G06F12/0862 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F12/0882 , G06F12/1009 , G06F2212/602 , G06F2212/65
摘要： Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application. Another aspect includes creating a page table entry corresponding to the memory page in the page table. Another aspect includes determining, by a data fetch width indicator determination logic, the data fetch width indicator for the memory page. Another aspect includes sending a notification of the data fetch width indicator from the data fetch width indicator determination logic to supervisory software. Another aspect includes setting the data fetch width indicator in the page table entry by the supervisory software based on the notification. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the memory page, fetching an amount of data from the memory page based on the data fetch width indicator.
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公开(公告)号：US09606855B1
公开(公告)日：2017-03-28
申请号：US14989397
申请日：2016-01-06
CPC分类号： G06F9/30076 , G06F9/3806 , G06F9/448 , G06F9/4484 , G06F21/00 , G06F21/52
摘要： Corruption of program stacks is detected by using guard words placed in the program stacks. A called routine executing on a processor checks a guard word in a stack of a calling routine. The checking determines whether the guard word has an expected value. Based on determining the guard word has an unexpected value, an indication of corruption of the stack is provided. Some routines, however, may not support use of guard words. Thus, routines that are interlinked may have differing protection capabilities. A determination is made as to the differing protection capabilities, an indication of the same is provided, and the routines are executed without failing due to the differing protection capabilities.
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公开(公告)号：US09582413B2
公开(公告)日：2017-02-28
申请号：US14560486
申请日：2014-12-04
CPC分类号： G06F12/023 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/3824 , G06F12/0646 , G06F13/1652 , G06F2212/1044 , G06F2212/251 , G06F2212/656
摘要： Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory reference instruction for accessing data of a first size at an address in the memory. The method determines an alignment size of the address in the memory. The method accesses the data of the first size in one or more groups of data by accessing each group of data block concurrently. The groups of data have sizes that are multiples of the alignment size.
摘要翻译： 实施例涉及访问存储器中的数据。 提供了一种用于访问耦合到处理器的存储器中的数据的方法。 该方法接收用于在存储器中的地址处访问第一大小的数据的存储器参考指令。 该方法确定存储器中地址的对齐大小。 该方法通过同时访问每组数据块来访问一组或多组数据中的第一大小的数据。 数据组的大小是对齐大小的倍数。
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