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公开(公告)号：US20230072305A1
公开(公告)日：2023-03-09
申请号：US17470686
申请日：2021-09-09
发明人： Kangguo Cheng , Juntao Li , Shogo Mochizuki , Choonghyun Lee
IPC分类号： H01L29/78 , H01L29/08 , H01L29/417 , H01L29/40 , H01L29/66
摘要： VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.
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72.发明授权公开(公告)号：US11562906B2
公开(公告)日：2023-01-24
申请号：US16265784
申请日：2019-02-01
发明人： Oleg Gluschenkov , Zuoguang Liu , Shogo Mochizuki , Hiroaki Niimi , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/285 , H01L29/08 , H01L29/24 , H01L29/267 , H01L29/78 , H01L29/66 , H01L21/768
摘要： Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.
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公开(公告)号：US11355649B2
公开(公告)日：2022-06-07
申请号：US17136160
申请日：2020-12-29
发明人： Choonghyun Lee , Kangguo Cheng , Juntao Li , Shogo Mochizuki
IPC分类号： H01L29/786 , H01L29/775 , H01L29/161 , H01L29/06 , H01L29/66 , H01L29/423
摘要： Embodiments of the invention are directed to a nanosheet field effect transistor (FET) having a nanosheet stack formed over a substrate. The nanosheet stack includes a plurality of channel nanosheets, wherein the plurality of channel nanosheets includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region. The first end region and the second end region include a first type of semiconductor material, wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant. The central region includes a second type of semiconductor material, wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.
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公开(公告)号：US20220173240A1
公开(公告)日：2022-06-02
申请号：US17671080
申请日：2022-02-14
发明人： Heng Wu , Shogo Mochizuki , Gen Tsutsui , Kangguo Cheng
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L21/8238 , H01L21/8234 , H01L27/24
摘要： A method of forming a vertical transport fin field effect transistor device is provided. The method includes forming vertical fins on a substrate, depositing a protective liner on the sidewalls of the vertical fins, and removing a portion of the substrate to form a support pillar beneath at least one of the vertical fins. The method further includes etching a cavity in the support pillar of the at least one of the vertical fins, and removing an additional portion of the substrate to form a plinth beneath the support pillar of the vertical fin. The method further includes growing a bottom source/drain layer on the substrate adjacent to the plinth, and forming a diffusion plug in the cavity, wherein the diffusion plug is configured to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar.
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公开(公告)号：US11316015B2
公开(公告)日：2022-04-26
申请号：US17134731
申请日：2020-12-28
发明人： Shogo Mochizuki , Kangguo Cheng , Choonghyun Lee , Juntao Li
IPC分类号： H01L29/76 , H01L29/161 , H01L21/308 , H01L29/78 , H01L29/66 , H01L29/51 , H01L21/28 , H01L29/08 , H01L29/10 , H01L21/768 , H01L21/3065 , H01L29/49
摘要： A method for forming the semiconductor device that includes forming an etch mask covering a drain side of the gate structure and the silicon containing fin structure; etching a source side of the silicon containing fin structure adjacent to the channel region; and forming a germanium containing semiconductor material on an etched sidewall of the silicon containing fin structure adjacent to the channel region. Germanium from the germanium containing semiconductor material is diffused into the channel region to provide a graded silicon germanium region in the channel region having germanium present at a highest concentration in the channel region at the source end of the channel region and a germanium deficient concentration at the drain end of the channel region.
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公开(公告)号：US11276781B2
公开(公告)日：2022-03-15
申请号：US16849101
申请日：2020-04-15
发明人： Heng Wu , Shogo Mochizuki , Gen Tsutsui , Kangguo Cheng
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L21/8238 , H01L21/8234 , H01L27/24
摘要： A method of forming a vertical transport fin field effect transistor device is provided. The method includes forming vertical fins on a substrate, depositing a protective liner on the sidewalls of the vertical fins, and removing a portion of the substrate to form a support pillar beneath at least one of the vertical fins. The method further includes etching a cavity in the support pillar of the at least one of the vertical fins, and removing an additional portion of the substrate to form a plinth beneath the support pillar of the vertical fin. The method further includes growing a bottom source/drain layer on the substrate adjacent to the plinth, and forming a diffusion plug in the cavity, wherein the diffusion plug is configured to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar.
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公开(公告)号：US11257934B2
公开(公告)日：2022-02-22
申请号：US16752817
申请日：2020-01-27
发明人： Kangguo Cheng , Juntao Li , ChoongHyun Lee , Shogo Mochizuki
摘要： A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.
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公开(公告)号：US11183427B2
公开(公告)日：2021-11-23
申请号：US16835882
申请日：2020-03-31
发明人： Huimei Zhou , Shogo Mochizuki , Gen Tsutsui , Ruqiang Bao
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/02 , H01L21/306 , H01L21/311
摘要： Semiconductor devices include a substrate layer and a semiconductor layer formed over the substrate layer. A dielectric layer fills a gap between the semiconductor layer and the substrate layer, on end faces of the semiconductor layer, and on a top surface of the semiconductor layer.
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公开(公告)号：US11088280B2
公开(公告)日：2021-08-10
申请号：US15814540
申请日：2017-11-16
发明人： Veeraraghavan S. Basker , Nicolas L. Breil , Oleg Gluschenkov , Shogo Mochizuki , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/201 , H01L29/205 , H01L29/207 , H01L29/66
摘要： The disclosure provides for a transistor which may include: a gate stack on a substrate, the gate stack including a gate dielectric and a gate electrode over the gate dielectric; a channel within the substrate and under the gate stack; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion and the second coefficient of diffusion is less than the third coefficient of diffusion.
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公开(公告)号：US20210151608A1
公开(公告)日：2021-05-20
申请号：US17136160
申请日：2020-12-29
发明人： Choonghyun Lee , Kangguo Cheng , Juntao Li , Shogo Mochizuki
IPC分类号： H01L29/786 , H01L29/775 , H01L29/161 , H01L29/06 , H01L29/66 , H01L29/423
摘要： Embodiments of the invention are directed to a nanosheet field effect transistor (FET) having a nanosheet stack formed over a substrate. The nanosheet stack includes a plurality of channel nanosheets, wherein the plurality of channel nanosheets includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region. The first end region and the second end region include a first type of semiconductor material, wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant. The central region includes a second type of semiconductor material, wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.
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