公开(公告)号：US20070218613A1

公开(公告)日：2007-09-20

申请号：US11657152

申请日：2007-01-24

申请人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21/8234

CPC分类号： H01L27/14647 ,  H01L27/1463 ,  H01L27/14689

摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.

摘要翻译： 提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。 该方法提供体硅（Si）衬底。 在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。 每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。 例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。 阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。 然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

公开(公告)号：US20080277701A1

公开(公告)日：2008-11-13

申请号：US11801320

申请日：2007-05-09

申请人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L31/113 ,  H01L31/18

CPC分类号： H01L27/14647 ,  H01L27/1463 ,  H01L27/14689

摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multifunction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set.

摘要翻译： 提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，具有相应的制造工艺。 彩色成像器单元阵列由体硅（Si）衬底形成，而不具有上覆的外延Si层。 在本体Si衬底中形成多个彩色成像器单元，其中每个彩色成像器单元包括光电二极管组和U形衬管。 光电二极管组包括形成为堆叠的多功能结构的第一，第二和第三光电二极管，而U形阱衬套将光电二极管组与阵列中的相邻光电二极管组完全隔离。 U形井衬管包括物理接口掺杂的井筒底部和第一壁。 阱衬底位于衬底和光电二极管组之间，并且第一壁物理地连接光电二极管组中每个光电二极管的每个掺杂层。

公开(公告)号：US06780700B2

公开(公告)日：2004-08-24

申请号：US10035503

申请日：2001-10-25

申请人： Katsuji Iguchi ,  Sheng Teng Hsu ,  Yoshi Ono ,  Jer-shen Maa

发明人： Katsuji Iguchi ,  Sheng Teng Hsu ,  Yoshi Ono ,  Jer-shen Maa

IPC分类号： H01L218238

CPC分类号： H01L21/823814

摘要： A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one active area and implanting ions of a second type to form a source region and a drain region in the other active area.

摘要翻译： 一种在硅衬底上形成MOS器件或CMOS器件的方法，包括制备衬底以包含其中具有器件有源区的导电区; 在有源区上形成栅电极; 在每个栅电极上沉积和形成栅电极侧壁绝缘体层; 注入第一类型的离子以在一个有效区域中形成源极区域和漏极区域，并且注入第二类型的离子，以在另一个有源区域中形成源极区域和漏极区域。

公开(公告)号：US06746902B2

公开(公告)日：2004-06-08

申请号：US10062319

申请日：2002-01-31

申请人： Jer-Shen Maa ,  Douglas James Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Douglas James Tweet ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/322 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02694 ,  Y10S438/933

摘要： A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 22%, by molecular weight; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.

摘要翻译： 形成Ge含量较高的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的Ge含量通过分子量等于或大于22％; 以约20keV至45keV之间的能量以约1.10 16 cm -2至5.10 16 cm -2的剂量将H +离子注入SiGe层; 热处理基板和SiGe层，以在约650℃至950℃的温度的惰性气氛中放松SiGe层约30秒至30分钟; 以及在弛豫的SiGe层上沉积拉伸应变硅层至约5nm至30nm的厚度。

公开(公告)号：US06682995B2

公开(公告)日：2004-01-27

申请号：US10317742

申请日：2002-12-11

申请人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L213205

CPC分类号： H01L29/456 ,  H01L21/28291 ,  H01L28/55 ,  H01L28/65

摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

摘要翻译： 已经提供了具有高温稳定性的导电阻挡层，其可用作铁电电容器电极。 该导电屏障允许在涉及退火的IC工艺中使用铱（Ir）金属。 已经发现，分离硅衬底与Ir膜与中间相邻的钽（Ta）膜非常有效地抑制层之间的扩散。 Ir防止退火过程中氧进入硅的相互扩散。 Ta或TaN层防止Ir扩散到硅中。 这种Ir / TaN结构保护了硅界面，从而使粘附，电导，小丘和剥离问题最小化。 使用覆盖Ir / TaN结构的Ti也有助于防止退火过程中的小丘形成。 还提供了形成多层Ir导电结构和Ir铁电电极的方法。

公开(公告)号：US06190963B1

公开(公告)日：2001-02-20

申请号：US09316661

申请日：1999-05-21

申请人： Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

发明人： Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55

摘要： An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir—M—O composite film barrier layer and an Ir—M—O composite film ferroelectric electrode are also provided.

摘要翻译： 已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜在氧气环境中耐高温退火。 当与由相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/屏障结构可用于非易失性FeRAM器件，DRAM，电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件。 还提供了形成Ir-M-O复合膜阻挡层和Ir-M-O复合膜铁电电极的方法。

公开(公告)号：US06537361B2

公开(公告)日：2003-03-25

申请号：US09822637

申请日：2001-03-30

申请人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L2122

CPC分类号： H01L21/02197 ,  C01G21/00 ,  C01P2002/86 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/31604 ,  H01L21/31691

摘要： A method of synthesizing a PGO spin-coating precursor solution includes utilizing the starting materials of lead acetate trihydrate (Pb(OAc)2•3H2O) and germanium alkoxide (Ge(OR)4(R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol) ethyl ether. The mixed solution of lead and di(ethylene glycol) ethyl ether is heated in an atmosphere of air at a temperature no greater than 185° C., and preferably no greater than 190° C. for a time period in a range of thirty minutes to four hours. During the heating step the color of the solution is monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol) ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. The process results in a PGO precursor solution suitable for use in spin-coating.

公开(公告)号：US06585821B1

公开(公告)日：2003-07-01

申请号：US10345636

申请日：2003-01-15

申请人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： C23C1616

CPC分类号： H01L21/02197 ,  C01G21/00 ,  C01P2002/86 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/31604 ,  H01L21/31691

摘要： A method of monitoring the synthesis of a PGO spin-coating precursor solution includes monitoring heating of the solution with a UV spectrometer and terminating the heating step when a solution property reaches a predetermined value. The method utilizes the starting materials of lead acetate trihydrate (Pb(OAc)2.3H2O) and germanium alkoxide (Ge(OR)4 (R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol)ethyl ether. The mixed solution of lead and di(ethylene glycol)ethyl ether is heated in an atmosphere of air at a temperature no greater than 190° C., and preferably no greater than 185° C. for a time period in a range of approximately eighty-five minutes. During the heating step the solution properties are monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol)ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. This heating step is also monitored with a UV spectrometer to determine when the heating step should be terminated. The process results in a PGO precursor solution suitable for use in spin-coating.

摘要翻译： 监测PGO旋涂前体溶液合成的方法包括用UV光谱仪监测溶液的加热，并且当溶液性能达到预定值时终止加热步骤。 该方法采用醋酸铅三水合物（Pb（OAc）2.3H2O）和烷氧基锗（Ge（OR）4（R = C2H5和CH（CH3）2））的原料。 有机溶剂是二（乙二醇）乙醚。 将铅和二（乙二醇）乙醚的混合溶液在不大于190℃，优选不大于185℃的空气气氛中加热约80℃的时间 -5分钟。 在加热步骤期间，监测溶液性质以确定反应何时完成，并且当所需产物的分解开始发生时。 然后将该溶液加入到二（乙二醇）二乙醚中以制备PGO旋涂溶液。 该第二步骤还需要将溶液加热至不高于190℃的温度，持续0.5至2.0小时的时间。 该加热步骤也用UV光谱仪监测，以确定加热步骤何时终止。 该方法产生适合用于旋涂的PGO前体溶液。

公开(公告)号：US06479304B1

公开(公告)日：2002-11-12

申请号：US09717993

申请日：2000-11-21

申请人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L28/75 ,  H01L21/28291 ,  H01L28/55 ,  H01L29/516

摘要： An Ir combination film has been provided that is useful in forming an electrode of a ferroelectric capacitor. The combination film includes tantalum and oxygen, as well as iridium. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying Ta or TaN layer, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. A method for forming an Ir composite film barrier layer and Ir composite film ferroelectric electrode are also provided.

摘要翻译： 已经提供了可用于形成铁电电容器的电极的Ir组合膜。 组合膜包括钽和氧，以及铱。 Ir组合膜有效防止氧气扩散，并且在氧气环境中耐高温退火。 当与下面的Ta或TaN层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 还提供了形成Ir复合膜阻挡层和Ir复合膜铁电电极的方法。

公开(公告)号：US06339245B1

公开(公告)日：2002-01-15

申请号：US09378653

申请日：1999-08-20

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656

摘要： A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces. A transistor, with an overhang structure, fabricated by the above-mentioned procedure is also provided.

摘要翻译： 提供了形成临时突出结构以屏蔽栅电极附近的源/漏边缘与沉积硅化金属的方法。 源极/漏极区域上的硅化物的生长保持受控，而在源极/漏极边缘附近的栅电极侧壁上不存在硅化金属。 所得到的硅化物层不具有干扰源极/漏极结区域的边缘增长。 通过用具有不同蚀刻选择性的两个绝缘体覆盖栅电极来形成突出结构。 顶绝缘体被各向异性地蚀刻，使得仅覆盖覆盖栅电极垂直侧壁的顶绝缘体保留。 暴露的底部绝缘体被各向同性地蚀刻以在顶部绝缘体和源极/漏极区域表面之间形成间隙。 当沉积硅化金属时，间隙防止金属沉积在栅电极和源/漏区表面之间。 还提供了通过上述程序制造的具有突出结构的晶体管。